scsi/aic7xxx/aic7xxx.h

4  * Copyright (c) 1994-2001 Justin T. Gibbs.
5  * Copyright (c) 2000-2001 Adaptec Inc.
19  * 3. Neither the names of the above-listed copyright holders nor the names
69 	(((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \
74 	((((ahc)->features & AHC_TWIN) != 0) \
78 	(SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B')
80 	SCSIID_OUR_ID((scb)->hscb->scsiid)
82 	SCSIID_TARGET((ahc), (scb)->hscb->scsiid)
84 	SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
86 	((scb)->hscb->lun & LID)
94       && (((scb)->flags & SCB_SILENT) != 0))
97 	(((scb)->flags & SCB_SILENT) != 0)
102 	(tcl & (AHC_NUM_LUNS - 1))
139  * Sequencer Control Blocks (SCBs) store per-transaction information.  Although
213 	AHC_SG_PRELOAD	= 0x00080,	/* Can perform auto-SG preload */
215 	AHC_MULTI_TID	= 0x00200,	/* Has bitmask of TIDs for select-in */
219 	AHC_MULTI_FUNC	= 0x02000,	/* Multi-Function Twin Channel Device */
225 	AHC_REMOVABLE	= 0x80000,	/* Hot-Swap supported */
229 	 * The real 7850 does not support Ultra modes, but there are
231 	 * they are using an Ultra capable chip (7859/7860).  We start
242 	 * the initiator role to allow multi-scsi-id target mode
268 	 * work during scsi->HostBus transfers.
287 	 * PCI 2.1 Retry failure on non-empty data fifo.
384  * complete abnormally (non-zero status byte).
400 	uint8_t  data_phase;		/* Data-In or Data-Out */
480 					 * 13->32.  We store them here
618  * Connection descriptor for select-in requests in target mode.
698  * Per-initiator current, goal and user transfer negotiation information. */
709  * for each initiator<->target mapping.  For the initiator role we pretend
721 	uint16_t	 ultraenb;	/* Using ultra sync rate  */
731 	u_int sxfr;	/* Value of the SXFR parameter for <= Ultra Chips */
732 #define		ULTRA_SXFR 0x100	/* Rate Requires Ultra Mode set */
755  * Phase -> name and message out response
770 	uint16_t device_flags[16];	/* words 0-15 */
775 #define		CFSYNCHISULTRA	0x0040	/* CFSYNCH is an ultra offset (2940AU)*/
776 #define		CFSYNCSINGLE	0x0080	/* Single-Transition signalling */
781 #define		CFWBCACHEENB	0x4000	/* Enable W-Behind Cache on disks */
782 #define		CFWBCACHENOP	0xc000	/* Don't touch W-Behind Cache */
795 #define		CFCTRL_A	0x0020	/* BIOS displays Ctrl-A message */
803 #define		CFBOOTCD	0x0800  /* Support Bootable CD-ROM */
811 #define		CFULTRAEN	0x0002	/* Ultra SCSI speed enable */
814 #define		CFSTERM		0x0004	/* SCSI low byte termination */
817 #define		CF284XSTERM     0x0020	/* SCSI low byte term (284x cards) */
824 #define		CFSELOWTERM	0x0800	/* Ultra2 secondary low term */
843 	uint16_t res_1[10];		/* words 20-29 */
924 	 * Per-target queue of untagged-transactions.  The
1048 	 * work-around a DMA bug for chips <= aic7880
1064 	 * We auto-disable parity error checking after seeing
1073 	/* Per-Unit descriptive information */
1210 	AHC_NEG_IF_NON_ASYNC,	/* Renegotiate so long as goal is non-async. */