Lines Matching refs:DSR
54 #define DSR 0x14 /* Status Reg */ macro
274 di_write_busy_wait(imxdi, DSR_CAF, DSR); in di_handle_valid_state()
324 di_write_busy_wait(imxdi, DSR_NVF, DSR); in di_handle_invalid_state()
326 di_write_busy_wait(imxdi, DSR_TCO, DSR); in di_handle_invalid_state()
333 return di_handle_valid_state(imxdi, __raw_readl(imxdi->ioaddr + DSR)); in di_handle_invalid_state()
376 DSR_MCO | DSR_TCO), DSR); in di_handle_invalid_and_failure_state()
378 dsr = readl(imxdi->ioaddr + DSR); in di_handle_invalid_and_failure_state()
390 di_write_busy_wait(imxdi, DSR_SVF, DSR); in di_handle_invalid_and_failure_state()
393 dsr = readl(imxdi->ioaddr + DSR); in di_handle_invalid_and_failure_state()
414 dsr = readl(imxdi->ioaddr + DSR); in di_handle_state()
478 writel(DSR_WEF, imxdi->ioaddr + DSR); in clear_write_error()
482 if ((readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0) in clear_write_error()
561 dsr = readl(imxdi->ioaddr + DSR); in dryice_rtc_set_time()
620 alarm->pending = (readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0; in dryice_rtc_read_alarm()
666 dsr = readl(imxdi->ioaddr + DSR); in dryice_irq()
732 di_write_wait(imxdi, DSR_CAF, DSR); in dryice_work()