136 	union FL_CTL_T fl_reg;  in nandc_bch_sel()  local
139 	fl_reg.d32 = 0;  in nandc_bch_sel()
140 	fl_reg.V6.rst = 1;  in nandc_bch_sel()
143 		nandc_writel(fl_reg.d32, NANDC_V9_FLCTL);  in nandc_bch_sel()
157 		nandc_writel(fl_reg.d32, NANDC_FLCTL);  in nandc_bch_sel()
188 	union FL_CTL_T fl_reg;  in nandc_xfer_start()  local
193 	fl_reg.d32 = 0;  in nandc_xfer_start()
195 		fl_reg.V9.flash_rdn = dir;  in nandc_xfer_start()
196 		fl_reg.V9.bypass = 1;  in nandc_xfer_start()
197 		fl_reg.V9.tr_count = 1;  in nandc_xfer_start()
198 		fl_reg.V9.async_tog_mix = 1;  in nandc_xfer_start()
199 		fl_reg.V9.cor_able = 1;  in nandc_xfer_start()
200 		fl_reg.V9.st_addr = 0;  in nandc_xfer_start()
201 		fl_reg.V9.page_num = (n_sec + 1) / 2;  in nandc_xfer_start()
203 		fl_reg.V9.flash_st_mod = 1;  in nandc_xfer_start()
225 				    fl_reg.V6.page_num * 1024,  in nandc_xfer_start()
229 				    fl_reg.V6.page_num * 64,  in nandc_xfer_start()
245 		nandc_writel(fl_reg.d32, NANDC_V9_FLCTL);  in nandc_xfer_start()
246 		fl_reg.V9.flash_st = 1;  in nandc_xfer_start()
247 		nandc_writel(fl_reg.d32, NANDC_V9_FLCTL);  in nandc_xfer_start()
254 		fl_reg.V6.rdn = dir;  in nandc_xfer_start()
255 		fl_reg.V6.dma = 1;  in nandc_xfer_start()
256 		fl_reg.V6.tr_count = 1;  in nandc_xfer_start()
257 		fl_reg.V6.async_tog_mix = 1;  in nandc_xfer_start()
258 		fl_reg.V6.cor_en = 1;  in nandc_xfer_start()
259 		fl_reg.V6.st_addr = 0;  in nandc_xfer_start()
278 		fl_reg.V6.page_num = (n_sec + 1) / 2;  in nandc_xfer_start()
285 						    fl_reg.V6.page_num * 1024,  in nandc_xfer_start()
289 						    fl_reg.V6.page_num * 64,  in nandc_xfer_start()
304 		nandc_writel(fl_reg.d32, NANDC_FLCTL);  in nandc_xfer_start()
305 		fl_reg.V6.start = 1;  in nandc_xfer_start()
306 		nandc_writel(fl_reg.d32, NANDC_FLCTL);  in nandc_xfer_start()
315 	union FL_CTL_T fl_reg;  in nandc_xfer_done()  local
324 				fl_reg.d32 = nandc_readl(NANDC_V9_FLCTL);  in nandc_xfer_done()
327 			} while (stat_reg.V9.mtrans_cnt < fl_reg.V9.page_num ||  in nandc_xfer_done()
328 				 fl_reg.V9.tr_rdy == 0);  in nandc_xfer_done()
332 					fl_reg.V9.page_num * 1024,  in nandc_xfer_done()
335 					fl_reg.V9.page_num * 64,  in nandc_xfer_done()
340 				fl_reg.d32 = nandc_readl(NANDC_V9_FLCTL);  in nandc_xfer_done()
342 			} while (fl_reg.V9.tr_rdy == 0);  in nandc_xfer_done()
345 					fl_reg.V9.page_num * 1024,  in nandc_xfer_done()
348 					fl_reg.V9.page_num * 64,  in nandc_xfer_done()
359 				fl_reg.d32 = nandc_readl(NANDC_FLCTL);  in nandc_xfer_done()
362 			} while (stat_reg.V6.mtrans_cnt < fl_reg.V6.page_num ||  in nandc_xfer_done()
363 				 !fl_reg.V6.tr_rdy);  in nandc_xfer_done()
368 					fl_reg.V6.page_num * 1024,  in nandc_xfer_done()
372 					fl_reg.V6.page_num * 64,  in nandc_xfer_done()
377 				fl_reg.d32 = nandc_readl(NANDC_FLCTL);  in nandc_xfer_done()
379 			} while (!fl_reg.V6.tr_rdy);  in nandc_xfer_done()
383 					fl_reg.V6.page_num * 1024, 1);  in nandc_xfer_done()
386 					fl_reg.V6.page_num * 64, 1);  in nandc_xfer_done()
392 				fl_reg.d32 = nandc_readl(NANDC_FLCTL);  in nandc_xfer_done()
393 			} while ((!fl_reg.V6.tr_rdy));  in nandc_xfer_done()