48 		ctl_reg.V6.wp = 1;  in nandc_init()
70 	tmp.V6.cs = 0x01 << chip_sel;  in nandc_flash_cs()
79 	tmp.V6.cs = 0;  in nandc_flash_de_cs()
80 	tmp.V6.flash_abort_clear = 0;  in nandc_flash_de_cs()
100 		if (tmp.V6.rdy != 0)  in nandc_wait_flash_ready()
140 	fl_reg.V6.rst = 1;  in nandc_bch_sel()
159 		tmp.V6.addr = 0x10;  in nandc_bch_sel()
160 		tmp.V6.bch_mode1 = 0;  in nandc_bch_sel()
162 			tmp.V6.bch_mode = 0;  in nandc_bch_sel()
164 			tmp.V6.bch_mode = 1;  in nandc_bch_sel()
166 			tmp.V6.bch_mode1 = 1;  in nandc_bch_sel()
167 			tmp.V6.bch_mode = 1;  in nandc_bch_sel()
169 				tmp.V6.bch_mode = 0;  in nandc_bch_sel()
171 		tmp.V6.rst = 1;  in nandc_bch_sel()
225 				    fl_reg.V6.page_num * 1024,  in nandc_xfer_start()
229 				    fl_reg.V6.page_num * 64,  in nandc_xfer_start()
250 		bch_reg.V6.addr = 0x10;  in nandc_xfer_start()
251 		bch_reg.V6.power_down = 0;  in nandc_xfer_start()
252 		bch_reg.V6.region = 0;  in nandc_xfer_start()
254 		fl_reg.V6.rdn = dir;  in nandc_xfer_start()
255 		fl_reg.V6.dma = 1;  in nandc_xfer_start()
256 		fl_reg.V6.tr_count = 1;  in nandc_xfer_start()
257 		fl_reg.V6.async_tog_mix = 1;  in nandc_xfer_start()
258 		fl_reg.V6.cor_en = 1;  in nandc_xfer_start()
259 		fl_reg.V6.st_addr = 0;  in nandc_xfer_start()
262 		master_reg.V6.bus_mode = 0;  in nandc_xfer_start()
278 		fl_reg.V6.page_num = (n_sec + 1) / 2;  in nandc_xfer_start()
285 						    fl_reg.V6.page_num * 1024,  in nandc_xfer_start()
289 						    fl_reg.V6.page_num * 64,  in nandc_xfer_start()
295 		master_reg.V6.incr_num = 16;  in nandc_xfer_start()
296 		master_reg.V6.burst = 7;  in nandc_xfer_start()
297 		master_reg.V6.hsize = 2;  in nandc_xfer_start()
298 		master_reg.V6.bus_mode = 1;  in nandc_xfer_start()
299 		master_reg.V6.ahb_wr = !dir;  in nandc_xfer_start()
300 		master_reg.V6.ahb_wr_st = 1;  in nandc_xfer_start()
305 		fl_reg.V6.start = 1;  in nandc_xfer_start()
354 		if (master_reg.V6.bus_mode != 0) {  in nandc_xfer_done()
357 		if (master_reg.V6.ahb_wr != 0) {  in nandc_xfer_done()
362 			} while (stat_reg.V6.mtrans_cnt < fl_reg.V6.page_num ||  in nandc_xfer_done()
363 				 !fl_reg.V6.tr_rdy);  in nandc_xfer_done()
368 					fl_reg.V6.page_num * 1024,  in nandc_xfer_done()
372 					fl_reg.V6.page_num * 64,  in nandc_xfer_done()
379 			} while (!fl_reg.V6.tr_rdy);  in nandc_xfer_done()
383 					fl_reg.V6.page_num * 1024, 1);  in nandc_xfer_done()
386 					fl_reg.V6.page_num * 64, 1);  in nandc_xfer_done()
393 			} while ((!fl_reg.V6.tr_rdy));  in nandc_xfer_done()
438 				if (bch_st_reg.V6.fail0 || bch_st_reg.V6.fail1) {  in nandc_xfer_data()
444 					max(bch_st_reg.V6.err_bits0 |  in nandc_xfer_data()
445 					    ((u32)bch_st_reg.V6.err_bits0_5 << 5),  in nandc_xfer_data()
446 					    bch_st_reg.V6.err_bits1 |  in nandc_xfer_data()
447 					    ((u32)bch_st_reg.V6.err_bits1_5 << 5));  in nandc_xfer_data()