80 	struct regmap *halt_map;  member
205 	ret = regmap_update_bits(wcss->halt_map,  in q6v5_wcss_start()
212 	ret = regmap_update_bits(wcss->halt_map,  in q6v5_wcss_start()
241 				    struct regmap *halt_map,  in q6v5_wcss_halt_axi_port()  argument
249 	ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);  in q6v5_wcss_halt_axi_port()
254 	regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);  in q6v5_wcss_halt_axi_port()
259 		ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);  in q6v5_wcss_halt_axi_port()
266 	ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);  in q6v5_wcss_halt_axi_port()
271 	regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);  in q6v5_wcss_halt_axi_port()
280 	q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss);  in q6v5_wcss_powerdown()
327 	q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_q6);  in q6v5_q6_powerdown()
498 	wcss->halt_map = syscon_node_to_regmap(args.np);  in q6v5_wcss_init_mmio()
500 	if (IS_ERR(wcss->halt_map))  in q6v5_wcss_init_mmio()
501 		return PTR_ERR(wcss->halt_map);  in q6v5_wcss_init_mmio()