41 static inline u32 zx_pwm_readl(struct zx_pwm_chip *zpc, unsigned int hwpwm,  in zx_pwm_readl()  argument
44 	return readl(zpc->base + (hwpwm + 1) * 0x10 + offset);  in zx_pwm_readl()
47 static inline void zx_pwm_writel(struct zx_pwm_chip *zpc, unsigned int hwpwm,  in zx_pwm_writel()  argument
50 	writel(value, zpc->base + (hwpwm + 1) * 0x10 + offset);  in zx_pwm_writel()
53 static void zx_pwm_set_mask(struct zx_pwm_chip *zpc, unsigned int hwpwm,  in zx_pwm_set_mask()  argument
58 	data = zx_pwm_readl(zpc, hwpwm, offset);  in zx_pwm_set_mask()
61 	zx_pwm_writel(zpc, hwpwm, offset, data);  in zx_pwm_set_mask()
73 	value = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE);  in zx_pwm_get_state()
88 	tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_PERIOD);  in zx_pwm_get_state()
92 	tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_DUTY);  in zx_pwm_get_state()
134 		zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_EN, 0);  in zx_pwm_config()
137 	zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_CLKDIV_MASK,  in zx_pwm_config()
139 	zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_PERIOD, period_cycles);  in zx_pwm_config()
140 	zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_DUTY, duty_cycles);  in zx_pwm_config()
144 		zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,  in zx_pwm_config()
160 		zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_POLAR,  in zx_pwm_apply()
178 			zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,  in zx_pwm_apply()
181 			zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,  in zx_pwm_apply()