78 	unsigned long duty;  member
122 	tmp = readl_relaxed(pc->base + pc->data->regs.duty);  in rockchip_pwm_get_state()
172 	unsigned long period, duty;  in rockchip_pwm_config()  local
184 	 * Since period and duty cycle registers have a width of 32  in rockchip_pwm_config()
192 	duty = DIV_ROUND_CLOSEST_ULL(div, dclk_div * pc->data->prescaler * NSEC_PER_SEC);  in rockchip_pwm_config()
196 	 * Lock the period and duty of previous configuration, then  in rockchip_pwm_config()
197 	 * change the duty and period, that would not be effective.  in rockchip_pwm_config()
262 	writel(duty, pc->base + pc->data->regs.duty);  in rockchip_pwm_config()
274 	 * the configuration of duty, period and polarity  in rockchip_pwm_config()
374 		.duty = 0x04,
389 		.duty = 0x08,
405 		.duty = 0x08,
421 		.duty = 0x08,