pinctrl/samsung/pinctrl-s3c64xx.c

1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
102 		.name		= id			\
112 		.eint_mask	= (1 << (pins)) - 1,	\
114 		.name		= id			\
126 		.name		= id			\
136 		.eint_mask	= (1 << (pins)) - 1,	\
138 		.name		= id			\
150 		.name		= id			\
159 		.name		= id			\
168 		.name		= id			\
180 		.name		= id			\
190 		.eint_mask	= (1 << (pins)) - 1,	\
192 		.name		= id			\
196  * struct s3c64xx_eint0_data - EINT0 common data
208  * struct s3c64xx_eint0_domain_data - EINT0 per-domain data
209  * @bank: pin bank related to the domain
213 	struct samsung_pin_bank *bank;  member
218  * struct s3c64xx_eint_gpio_data - GPIO EINT data
252 		return -EINVAL;  in s3c64xx_irq_get_trigger()
260 	/* Edge- and level-triggered interrupts need different handlers */  in s3c64xx_irq_set_handler()
268 					struct samsung_pin_bank *bank, int pin)  in s3c64xx_irq_set_function()  argument
270 	const struct samsung_pin_bank_type *bank_type = bank->type;  in s3c64xx_irq_set_function()
278 	reg = d->virt_base + bank->pctl_offset;  in s3c64xx_irq_set_function()
280 	if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) {  in s3c64xx_irq_set_function()
281 		/* 4-bit bank type with 2 con regs */  in s3c64xx_irq_set_function()
283 		shift -= 8;  in s3c64xx_irq_set_function()
286 	shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC];  in s3c64xx_irq_set_function()
287 	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;  in s3c64xx_irq_set_function()
289 	spin_lock_irqsave(&bank->slock, flags);  in s3c64xx_irq_set_function()
293 	val |= bank->eint_func << shift;  in s3c64xx_irq_set_function()
296 	spin_unlock_irqrestore(&bank->slock, flags);  in s3c64xx_irq_set_function()
300  * Functions for EINT GPIO configuration (EINT groups 1-9)
305 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);  in s3c64xx_gpio_irq_set_mask()  local
306 	struct samsung_pinctrl_drv_data *d = bank->drvdata;  in s3c64xx_gpio_irq_set_mask()
307 	unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;  in s3c64xx_gpio_irq_set_mask()
308 	void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset);  in s3c64xx_gpio_irq_set_mask()
331 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);  in s3c64xx_gpio_irq_ack()  local
332 	struct samsung_pinctrl_drv_data *d = bank->drvdata;  in s3c64xx_gpio_irq_ack()
333 	unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;  in s3c64xx_gpio_irq_ack()
334 	void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset);  in s3c64xx_gpio_irq_ack()
341 	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);  in s3c64xx_gpio_irq_set_type()  local
342 	struct samsung_pinctrl_drv_data *d = bank->drvdata;  in s3c64xx_gpio_irq_set_type()
351 		return -EINVAL;  in s3c64xx_gpio_irq_set_type()
357 	reg = d->virt_base + EINTCON_REG(bank->eint_offset);  in s3c64xx_gpio_irq_set_type()
358 	shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;  in s3c64xx_gpio_irq_set_type()
366 	s3c64xx_irq_set_function(d, bank, irqd->hwirq);  in s3c64xx_gpio_irq_set_type()
375 	.name		= "GPIO",
385 	struct samsung_pin_bank *bank = h->host_data;  in s3c64xx_gpio_irq_map()  local
387 	if (!(bank->eint_mask & (1 << hw)))  in s3c64xx_gpio_irq_map()
388 		return -EINVAL;  in s3c64xx_gpio_irq_map()
392 	irq_set_chip_data(virq, bank);  in s3c64xx_gpio_irq_map()
409 	struct samsung_pinctrl_drv_data *drvdata = data->drvdata;  in s3c64xx_eint_gpio_irq()
419 		svc = readl(drvdata->virt_base + SERVICE_REG);  in s3c64xx_eint_gpio_irq()
431 				pin -= 8;  in s3c64xx_eint_gpio_irq()
434 		virq = irq_linear_revmap(data->domains[group], pin);  in s3c64xx_eint_gpio_irq()
448  * s3c64xx_eint_gpio_init() - setup handling of external gpio interrupts.
454 	struct samsung_pin_bank *bank;  in s3c64xx_eint_gpio_init()  local
455 	struct device *dev = d->dev;  in s3c64xx_eint_gpio_init()
459 	if (!d->irq) {  in s3c64xx_eint_gpio_init()
461 		return -EINVAL;  in s3c64xx_eint_gpio_init()
465 	bank = d->pin_banks;  in s3c64xx_eint_gpio_init()
466 	for (i = 0; i < d->nr_banks; ++i, ++bank) {  in s3c64xx_eint_gpio_init()
470 		if (bank->eint_type != EINT_TYPE_GPIO)  in s3c64xx_eint_gpio_init()
473 		mask = bank->eint_mask;  in s3c64xx_eint_gpio_init()
476 		bank->irq_domain = irq_domain_add_linear(bank->of_node,  in s3c64xx_eint_gpio_init()
477 					nr_eints, &s3c64xx_gpio_irqd_ops, bank);  in s3c64xx_eint_gpio_init()
478 		if (!bank->irq_domain) {  in s3c64xx_eint_gpio_init()
480 			return -ENXIO;  in s3c64xx_eint_gpio_init()
489 		return -ENOMEM;  in s3c64xx_eint_gpio_init()
490 	data->drvdata = d;  in s3c64xx_eint_gpio_init()
492 	bank = d->pin_banks;  in s3c64xx_eint_gpio_init()
494 	for (i = 0; i < d->nr_banks; ++i, ++bank) {  in s3c64xx_eint_gpio_init()
495 		if (bank->eint_type != EINT_TYPE_GPIO)  in s3c64xx_eint_gpio_init()
498 		data->domains[nr_domains++] = bank->irq_domain;  in s3c64xx_eint_gpio_init()
501 	irq_set_chained_handler_and_data(d->irq, s3c64xx_eint_gpio_irq, data);  in s3c64xx_eint_gpio_init()
507  * Functions for configuration of EINT0 wake-up interrupts
514 	struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;  in s3c64xx_eint0_irq_set_mask()
517 	val = readl(d->virt_base + EINT0MASK_REG);  in s3c64xx_eint0_irq_set_mask()
519 		val |= 1 << ddata->eints[irqd->hwirq];  in s3c64xx_eint0_irq_set_mask()
521 		val &= ~(1 << ddata->eints[irqd->hwirq]);  in s3c64xx_eint0_irq_set_mask()
522 	writel(val, d->virt_base + EINT0MASK_REG);  in s3c64xx_eint0_irq_set_mask()
539 	struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;  in s3c64xx_eint0_irq_ack()
541 	writel(1 << ddata->eints[irqd->hwirq],  in s3c64xx_eint0_irq_ack()
542 					d->virt_base + EINT0PEND_REG);  in s3c64xx_eint0_irq_ack()
549 	struct samsung_pin_bank *bank = ddata->bank;  in s3c64xx_eint0_irq_set_type()  local
550 	struct samsung_pinctrl_drv_data *d = bank->drvdata;  in s3c64xx_eint0_irq_set_type()
559 		return -EINVAL;  in s3c64xx_eint0_irq_set_type()
565 	reg = d->virt_base + EINT0CON0_REG;  in s3c64xx_eint0_irq_set_type()
566 	shift = ddata->eints[irqd->hwirq];  in s3c64xx_eint0_irq_set_type()
569 		shift -= EINT_MAX_PER_REG;  in s3c64xx_eint0_irq_set_type()
578 	s3c64xx_irq_set_function(d, bank, irqd->hwirq);  in s3c64xx_eint0_irq_set_type()
587 	.name		= "EINT0",
598 	struct samsung_pinctrl_drv_data *drvdata = data->drvdata;  in s3c64xx_irq_demux_eint()
603 	pend = readl(drvdata->virt_base + EINT0PEND_REG);  in s3c64xx_irq_demux_eint()
604 	mask = readl(drvdata->virt_base + EINT0MASK_REG);  in s3c64xx_irq_demux_eint()
612 		irq = fls(pend) - 1;  in s3c64xx_irq_demux_eint()
614 		virq = irq_linear_revmap(data->domains[irq], data->pins[irq]);  in s3c64xx_irq_demux_eint()
657 	struct s3c64xx_eint0_domain_data *ddata = h->host_data;  in s3c64xx_eint0_irq_map()
658 	struct samsung_pin_bank *bank = ddata->bank;  in s3c64xx_eint0_irq_map()  local
660 	if (!(bank->eint_mask & (1 << hw)))  in s3c64xx_eint0_irq_map()
661 		return -EINVAL;  in s3c64xx_eint0_irq_map()
680 	{ .compatible = "samsung,s3c64xx-wakeup-eint", },
685  * s3c64xx_eint_eint0_init() - setup handling of external wakeup interrupts.
690 	struct device *dev = d->dev;  in s3c64xx_eint_eint0_init()
693 	struct samsung_pin_bank *bank;  in s3c64xx_eint_eint0_init()  local
697 	for_each_child_of_node(dev->of_node, np) {  in s3c64xx_eint_eint0_init()
704 		return -ENODEV;  in s3c64xx_eint_eint0_init()
709 		return -ENOMEM;  in s3c64xx_eint_eint0_init()
711 	data->drvdata = d;  in s3c64xx_eint_eint0_init()
720 			return -ENXIO;  in s3c64xx_eint_eint0_init()
729 	bank = d->pin_banks;  in s3c64xx_eint_eint0_init()
730 	for (i = 0; i < d->nr_banks; ++i, ++bank) {  in s3c64xx_eint_eint0_init()
737 		if (bank->eint_type != EINT_TYPE_WKUP)  in s3c64xx_eint_eint0_init()
740 		mask = bank->eint_mask;  in s3c64xx_eint_eint0_init()
746 			return -ENOMEM;  in s3c64xx_eint_eint0_init()
747 		ddata->bank = bank;  in s3c64xx_eint_eint0_init()
749 		bank->irq_domain = irq_domain_add_linear(bank->of_node,  in s3c64xx_eint_eint0_init()
751 		if (!bank->irq_domain) {  in s3c64xx_eint_eint0_init()
753 			return -ENXIO;  in s3c64xx_eint_eint0_init()
756 		irq = bank->eint_offset;  in s3c64xx_eint_eint0_init()
757 		mask = bank->eint_mask;  in s3c64xx_eint_eint0_init()
761 			data->domains[irq] = bank->irq_domain;  in s3c64xx_eint_eint0_init()
762 			data->pins[irq] = pin;  in s3c64xx_eint_eint0_init()
763 			ddata->eints[pin] = irq;  in s3c64xx_eint_eint0_init()
771 /* pin banks of s3c64xx pin-controller 0 */
794  * one gpio/pin-mux/pinconfig controller.
798 		/* pin-controller instance 1 data */