Lines Matching +full:0 +full:x0c00
34 #define U300_SYSCON_PMC1LR 0x007C
35 #define U300_SYSCON_PMC1LR_MASK 0xFFFF
36 #define U300_SYSCON_PMC1LR_CDI_MASK 0xC000
37 #define U300_SYSCON_PMC1LR_CDI_CDI 0x0000
38 #define U300_SYSCON_PMC1LR_CDI_EMIF 0x4000
40 #define U300_SYSCON_PMC1LR_CDI_CDI2 0x8000
41 #define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO 0xC000
43 #define U300_SYSCON_PMC1LR_CDI_GPIO 0x8000
44 #define U300_SYSCON_PMC1LR_CDI_WCDMA 0xC000
46 #define U300_SYSCON_PMC1LR_PDI_MASK 0x3000
47 #define U300_SYSCON_PMC1LR_PDI_PDI 0x0000
48 #define U300_SYSCON_PMC1LR_PDI_EGG 0x1000
49 #define U300_SYSCON_PMC1LR_PDI_WCDMA 0x3000
50 #define U300_SYSCON_PMC1LR_MMCSD_MASK 0x0C00
51 #define U300_SYSCON_PMC1LR_MMCSD_MMCSD 0x0000
52 #define U300_SYSCON_PMC1LR_MMCSD_MSPRO 0x0400
53 #define U300_SYSCON_PMC1LR_MMCSD_DSP 0x0800
54 #define U300_SYSCON_PMC1LR_MMCSD_WCDMA 0x0C00
55 #define U300_SYSCON_PMC1LR_ETM_MASK 0x0300
56 #define U300_SYSCON_PMC1LR_ETM_ACC 0x0000
57 #define U300_SYSCON_PMC1LR_ETM_APP 0x0100
58 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK 0x00C0
59 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC 0x0000
60 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF 0x0040
61 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM 0x0080
62 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB 0x00C0
63 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK 0x0030
64 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC 0x0000
65 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF 0x0010
66 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM 0x0020
67 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI 0x0030
68 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK 0x000C
69 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC 0x0000
70 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF 0x0004
71 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM 0x0008
72 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI 0x000C
73 #define U300_SYSCON_PMC1LR_EMIF_1_MASK 0x0003
74 #define U300_SYSCON_PMC1LR_EMIF_1_STATIC 0x0000
75 #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 0x0001
76 #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 0x0002
77 #define U300_SYSCON_PMC1LR_EMIF_1 0x0003
79 #define U300_SYSCON_PMC1HR 0x007E
80 #define U300_SYSCON_PMC1HR_MASK 0xFFFF
81 #define U300_SYSCON_PMC1HR_MISC_2_MASK 0xC000
82 #define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO 0x0000
83 #define U300_SYSCON_PMC1HR_MISC_2_MSPRO 0x4000
84 #define U300_SYSCON_PMC1HR_MISC_2_DSP 0x8000
85 #define U300_SYSCON_PMC1HR_MISC_2_AAIF 0xC000
86 #define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK 0x3000
87 #define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO 0x0000
88 #define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF 0x1000
89 #define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP 0x2000
90 #define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF 0x3000
91 #define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK 0x0C00
92 #define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO 0x0000
93 #define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC 0x0400
94 #define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP 0x0800
95 #define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF 0x0C00
96 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK 0x0300
97 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO 0x0000
98 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI 0x0100
99 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF 0x0300
100 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK 0x00C0
101 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO 0x0000
102 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI 0x0040
103 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF 0x00C0
104 #define U300_SYSCON_PMC1HR_APP_SPI_2_MASK 0x0030
105 #define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO 0x0000
106 #define U300_SYSCON_PMC1HR_APP_SPI_2_SPI 0x0010
107 #define U300_SYSCON_PMC1HR_APP_SPI_2_DSP 0x0020
108 #define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF 0x0030
109 #define U300_SYSCON_PMC1HR_APP_UART0_2_MASK 0x000C
110 #define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO 0x0000
111 #define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 0x0004
112 #define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS 0x0008
113 #define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF 0x000C
114 #define U300_SYSCON_PMC1HR_APP_UART0_1_MASK 0x0003
115 #define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO 0x0000
116 #define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 0x0001
117 #define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF 0x0003
119 #define U300_SYSCON_PMC2R 0x100
120 #define U300_SYSCON_PMC2R_APP_MISC_0_MASK 0x00C0
121 #define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO 0x0000
122 #define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM 0x0040
123 #define U300_SYSCON_PMC2R_APP_MISC_0_MMC 0x0080
124 #define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 0x00C0
125 #define U300_SYSCON_PMC2R_APP_MISC_1_MASK 0x0300
126 #define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO 0x0000
127 #define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM 0x0100
128 #define U300_SYSCON_PMC2R_APP_MISC_1_MMC 0x0200
129 #define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 0x0300
130 #define U300_SYSCON_PMC2R_APP_MISC_2_MASK 0x0C00
131 #define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO 0x0000
132 #define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM 0x0400
133 #define U300_SYSCON_PMC2R_APP_MISC_2_MMC 0x0800
134 #define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 0x0C00
135 #define U300_SYSCON_PMC2R_APP_MISC_3_MASK 0x3000
136 #define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO 0x0000
137 #define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM 0x1000
138 #define U300_SYSCON_PMC2R_APP_MISC_3_MMC 0x2000
139 #define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 0x3000
140 #define U300_SYSCON_PMC2R_APP_MISC_4_MASK 0xC000
141 #define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO 0x0000
142 #define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM 0x4000
143 #define U300_SYSCON_PMC2R_APP_MISC_4_MMC 0x8000
144 #define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO 0xC000
146 #define U300_SYSCON_PMC3R 0x10C
147 #define U300_SYSCON_PMC3R_APP_MISC_11_MASK 0xC000
148 #define U300_SYSCON_PMC3R_APP_MISC_11_SPI 0x4000
149 #define U300_SYSCON_PMC3R_APP_MISC_10_MASK 0x3000
150 #define U300_SYSCON_PMC3R_APP_MISC_10_SPI 0x1000
152 #define U300_SYSCON_PMC4R 0x168
153 #define U300_SYSCON_PMC4R_APP_MISC_12_MASK 0x0003
154 #define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO 0x0000
155 #define U300_SYSCON_PMC4R_APP_MISC_13_MASK 0x000C
156 #define U300_SYSCON_PMC4R_APP_MISC_13_CDI 0x0000
157 #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA 0x0004
158 #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 0x0008
159 #define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO 0x000C
160 #define U300_SYSCON_PMC4R_APP_MISC_14_MASK 0x0030
161 #define U300_SYSCON_PMC4R_APP_MISC_14_CDI 0x0000
162 #define U300_SYSCON_PMC4R_APP_MISC_14_SMIA 0x0010
163 #define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 0x0020
164 #define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO 0x0030
165 #define U300_SYSCON_PMC4R_APP_MISC_16_MASK 0x0300
166 #define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 0x0000
167 #define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS 0x0100
168 #define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N 0x0200
174 * edges of the silicon, finger by finger. LTCORNER upper left is pad 0.
177 * 0 ..... 104
189 PINCTRL_PIN(0, "P PAD VDD 28"),
244 PINCTRL_PIN(55, "PO RF WCDMA EN 0"),
262 PINCTRL_PIN(73, "PO ANT SW 0"),
273 PINCTRL_PIN(84, "PO SYS 0 CLK"),
274 PINCTRL_PIN(85, "PI SYS 0 CLKRQ"),
276 PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"),
360 PINCTRL_PIN(170, "MMC DATA 0"),
544 PINCTRL_PIN(352, "PI EMU MODE 0"),
547 PINCTRL_PIN(355, "PO EMIF 0 SD CS N"),
548 PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"),
549 PINCTRL_PIN(357, "PO EMIF 0 SD WE N"),
554 PINCTRL_PIN(362, "PO EMIF 0 SD CKE"),
555 PINCTRL_PIN(363, "PO EMIF 0 SD DQML"),
556 PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"),
557 PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"),
558 PINCTRL_PIN(366, "PIO EMIF 0 D15"),
559 PINCTRL_PIN(367, "PO EMIF 0 A15"),
560 PINCTRL_PIN(368, "PIO EMIF 0 D14"),
561 PINCTRL_PIN(369, "PO EMIF 0 A14"),
562 PINCTRL_PIN(370, "PIO EMIF 0 D13"),
563 PINCTRL_PIN(371, "PO EMIF 0 A13"),
568 PINCTRL_PIN(376, "PIO EMIF 0 D12"),
569 PINCTRL_PIN(377, "PO EMIF 0 A12"),
570 PINCTRL_PIN(378, "PIO EMIF 0 D11"),
571 PINCTRL_PIN(379, "PO EMIF 0 A11"),
572 PINCTRL_PIN(380, "PIO EMIF 0 D10"),
573 PINCTRL_PIN(381, "PO EMIF 0 A10"),
574 PINCTRL_PIN(382, "PIO EMIF 0 D09"),
575 PINCTRL_PIN(383, "PO EMIF 0 A09"),
576 PINCTRL_PIN(384, "PIO EMIF 0 D08"),
577 PINCTRL_PIN(385, "PO EMIF 0 A08"),
578 PINCTRL_PIN(386, "PIO EMIF 0 D07"),
579 PINCTRL_PIN(387, "PO EMIF 0 A07"),
585 PINCTRL_PIN(393, "PIO EMIF 0 D06"),
586 PINCTRL_PIN(394, "PO EMIF 0 A06"),
587 PINCTRL_PIN(395, "PIO EMIF 0 D05"),
588 PINCTRL_PIN(396, "PO EMIF 0 A05"),
589 PINCTRL_PIN(397, "PIO EMIF 0 D04"),
590 PINCTRL_PIN(398, "PO EMIF 0 A04"),
598 PINCTRL_PIN(406, "PIO EMIF 0 D03"),
599 PINCTRL_PIN(407, "PO EMIF 0 A03"),
602 PINCTRL_PIN(410, "PIO EMIF 0 D02"),
603 PINCTRL_PIN(411, "PO EMIF 0 A02"),
604 PINCTRL_PIN(412, "PIO EMIF 0 D01"),
609 PINCTRL_PIN(417, "PO EMIF 0 A01"),
610 PINCTRL_PIN(418, "PIO EMIF 0 D00"),
611 PINCTRL_PIN(419, "IF 0 SD CLK"),
717 static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63,
741 {0, 0},
742 {0, 0},
743 {0, 0},
744 {0, 0},
745 {0, 0},
763 {0, 0},
764 {0, 0},
765 {0, 0},
766 {0, 0},
770 {0, 0},
777 {0, 0},
778 {0, 0},
779 {0, 0},
784 {0, 0},
785 {0, 0},
786 {0, 0},
792 {0, 0},
801 {0, 0},
802 {0, 0},
803 {0, 0}
856 return 0; in u300_get_group_pins()
943 for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) { in u300_pmx_endisable()
947 val = 0; in u300_pmx_endisable()
950 if (mask != 0) { in u300_pmx_endisable()
966 if (selector == 0) in u300_pmx_set_mux()
967 return 0; in u300_pmx_set_mux()
972 return 0; in u300_pmx_set_mux()
992 return 0; in u300_pmx_get_groups()
1027 for (i = 0; i < num_configs; i++) { in u300_pin_config_set()
1036 return 0; in u300_pin_config_set()
1066 upmx->virtbase = devm_platform_ioremap_resource(pdev, 0); in u300_pmx_probe()
1080 return 0; in u300_pmx_probe()