Lines Matching +full:wakeup +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0-only
9 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
10 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
33 #include <linux/pinctrl/pinconf-generic.h>
36 #include "pinctrl-utils.h"
37 #include "pinctrl-amd.h"
45 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_get_direction()
46 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_direction()
47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_get_direction()
61 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_direction_input()
62 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_input()
64 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_input()
65 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_direction_input()
77 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_direction_output()
78 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_output()
84 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_output()
85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_direction_output()
96 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_get_value()
97 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_value()
98 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_get_value()
109 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_set_value()
110 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_value()
115 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_value()
116 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_set_value()
128 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_set_debounce()
129 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
170 ret = -EINVAL; in amd_gpio_set_debounce()
178 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
179 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_set_debounce()
185 unsigned long config) in amd_gpio_set_config() argument
189 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) in amd_gpio_set_config()
190 return -ENOTSUPP; in amd_gpio_set_config()
192 debounce = pinconf_to_config_argument(config); in amd_gpio_set_config()
218 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { in amd_gpio_dbg_show()
244 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_dbg_show()
245 pin_reg = readl(gpio_dev->base + i * 4); in amd_gpio_dbg_show()
246 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_dbg_show()
283 wake_cntrl0 = "enable wakeup in S0i3 state|"; in amd_gpio_dbg_show()
285 wake_cntrl0 = "disable wakeup in S0i3 state|"; in amd_gpio_dbg_show()
288 wake_cntrl1 = "enable wakeup in S3 state|"; in amd_gpio_dbg_show()
290 wake_cntrl1 = "disable wakeup in S3 state|"; in amd_gpio_dbg_show()
293 wake_cntrl2 = "enable wakeup in S4/S5 state|"; in amd_gpio_dbg_show()
295 wake_cntrl2 = "disable wakeup in S4/S5 state|"; in amd_gpio_dbg_show()
298 pull_up_enable = "pull-up is enabled|"; in amd_gpio_dbg_show()
300 pull_up_sel = "8k pull-up|"; in amd_gpio_dbg_show()
302 pull_up_sel = "4k pull-up|"; in amd_gpio_dbg_show()
304 pull_up_enable = "pull-up is disabled|"; in amd_gpio_dbg_show()
309 pull_down_enable = "pull-down is enabled|"; in amd_gpio_dbg_show()
311 pull_down_enable = "Pull-down is disabled|"; in amd_gpio_dbg_show()
351 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_enable()
352 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
355 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
356 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_enable()
366 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_disable()
367 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
370 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
371 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_disable()
381 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_mask()
382 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
384 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
385 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_mask()
395 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_unmask()
396 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
398 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
399 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_unmask()
409 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_eoi()
410 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); in amd_gpio_irq_eoi()
412 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); in amd_gpio_irq_eoi()
413 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_eoi()
424 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_set_type()
425 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
467 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); in amd_gpio_irq_set_type()
468 ret = -EINVAL; in amd_gpio_irq_set_type()
491 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
492 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) in amd_gpio_irq_set_type()
494 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
495 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_set_type()
526 struct gpio_chip *gc = &gpio_dev->gc; in amd_gpio_irq_handler()
535 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_handler()
536 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); in amd_gpio_irq_handler()
538 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); in amd_gpio_irq_handler()
539 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_handler()
541 /* Bit 0-45 contain the relevant status bits */ in amd_gpio_irq_handler()
542 status &= (1ULL << 46) - 1; in amd_gpio_irq_handler()
543 regs = gpio_dev->base; in amd_gpio_irq_handler()
555 irq = irq_find_mapping(gc->irq.domain, irqnr + i); in amd_gpio_irq_handler()
567 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_handler()
571 dev_dbg(&gpio_dev->pdev->dev, in amd_gpio_irq_handler()
576 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_handler()
582 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_handler()
583 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); in amd_gpio_irq_handler()
585 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); in amd_gpio_irq_handler()
586 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_handler()
595 return gpio_dev->ngroups; in amd_get_groups_count()
603 return gpio_dev->groups[group].name; in amd_get_group_name()
613 *pins = gpio_dev->groups[group].pins; in amd_get_group_pins()
614 *num_pins = gpio_dev->groups[group].npins; in amd_get_group_pins()
630 unsigned long *config) in amd_pinconf_get() argument
636 enum pin_config_param param = pinconf_to_config_param(*config); in amd_pinconf_get()
638 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_pinconf_get()
639 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_get()
640 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_pinconf_get()
659 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", in amd_pinconf_get()
661 return -ENOTSUPP; in amd_pinconf_get()
664 *config = pinconf_to_config_packed(param, arg); in amd_pinconf_get()
680 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_pinconf_set()
684 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_set()
712 dev_err(&gpio_dev->pdev->dev, in amd_pinconf_set()
713 "Invalid config param %04x\n", param); in amd_pinconf_set()
714 ret = -ENOTSUPP; in amd_pinconf_set()
717 writel(pin_reg, gpio_dev->base + pin*4); in amd_pinconf_set()
719 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_pinconf_set()
726 unsigned long *config) in amd_pinconf_group_get() argument
736 if (amd_pinconf_get(pctldev, pins[0], config)) in amd_pinconf_group_get()
737 return -ENOTSUPP; in amd_pinconf_group_get()
755 return -ENOTSUPP; in amd_pinconf_group_set()
769 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; in amd_gpio_irq_init()
778 for (i = 0; i < desc->npins; i++) { in amd_gpio_irq_init()
779 int pin = desc->pins[i].number; in amd_gpio_irq_init()
780 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); in amd_gpio_irq_init()
785 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_init()
787 pin_reg = readl(gpio_dev->base + i * 4); in amd_gpio_irq_init()
789 writel(pin_reg, gpio_dev->base + i * 4); in amd_gpio_irq_init()
791 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_init()
798 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); in amd_gpio_should_save()
807 if (pd->mux_owner || pd->gpio_owner || in amd_gpio_should_save()
808 gpiochip_line_is_irq(&gpio_dev->gc, pin)) in amd_gpio_should_save()
817 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; in amd_gpio_suspend()
821 for (i = 0; i < desc->npins; i++) { in amd_gpio_suspend()
822 int pin = desc->pins[i].number; in amd_gpio_suspend()
827 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_suspend()
828 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; in amd_gpio_suspend()
829 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_suspend()
838 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; in amd_gpio_resume()
842 for (i = 0; i < desc->npins; i++) { in amd_gpio_resume()
843 int pin = desc->pins[i].number; in amd_gpio_resume()
848 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_resume()
849 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; in amd_gpio_resume()
850 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); in amd_gpio_resume()
851 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_resume()
879 gpio_dev = devm_kzalloc(&pdev->dev, in amd_gpio_probe()
882 return -ENOMEM; in amd_gpio_probe()
884 raw_spin_lock_init(&gpio_dev->lock); in amd_gpio_probe()
888 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); in amd_gpio_probe()
889 return -EINVAL; in amd_gpio_probe()
892 gpio_dev->base = devm_ioremap(&pdev->dev, res->start, in amd_gpio_probe()
894 if (!gpio_dev->base) in amd_gpio_probe()
895 return -ENOMEM; in amd_gpio_probe()
902 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, in amd_gpio_probe()
903 sizeof(*gpio_dev->saved_regs), in amd_gpio_probe()
905 if (!gpio_dev->saved_regs) in amd_gpio_probe()
906 return -ENOMEM; in amd_gpio_probe()
909 gpio_dev->pdev = pdev; in amd_gpio_probe()
910 gpio_dev->gc.get_direction = amd_gpio_get_direction; in amd_gpio_probe()
911 gpio_dev->gc.direction_input = amd_gpio_direction_input; in amd_gpio_probe()
912 gpio_dev->gc.direction_output = amd_gpio_direction_output; in amd_gpio_probe()
913 gpio_dev->gc.get = amd_gpio_get_value; in amd_gpio_probe()
914 gpio_dev->gc.set = amd_gpio_set_value; in amd_gpio_probe()
915 gpio_dev->gc.set_config = amd_gpio_set_config; in amd_gpio_probe()
916 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; in amd_gpio_probe()
918 gpio_dev->gc.base = -1; in amd_gpio_probe()
919 gpio_dev->gc.label = pdev->name; in amd_gpio_probe()
920 gpio_dev->gc.owner = THIS_MODULE; in amd_gpio_probe()
921 gpio_dev->gc.parent = &pdev->dev; in amd_gpio_probe()
922 gpio_dev->gc.ngpio = resource_size(res) / 4; in amd_gpio_probe()
924 gpio_dev->gc.of_node = pdev->dev.of_node; in amd_gpio_probe()
927 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; in amd_gpio_probe()
928 gpio_dev->groups = kerncz_groups; in amd_gpio_probe()
929 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); in amd_gpio_probe()
931 amd_pinctrl_desc.name = dev_name(&pdev->dev); in amd_gpio_probe()
932 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, in amd_gpio_probe()
934 if (IS_ERR(gpio_dev->pctrl)) { in amd_gpio_probe()
935 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in amd_gpio_probe()
936 return PTR_ERR(gpio_dev->pctrl); in amd_gpio_probe()
942 girq = &gpio_dev->gc.irq; in amd_gpio_probe()
943 girq->chip = &amd_gpio_irqchip; in amd_gpio_probe()
945 girq->parent_handler = NULL; in amd_gpio_probe()
946 girq->num_parents = 0; in amd_gpio_probe()
947 girq->parents = NULL; in amd_gpio_probe()
948 girq->default_type = IRQ_TYPE_NONE; in amd_gpio_probe()
949 girq->handler = handle_simple_irq; in amd_gpio_probe()
951 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); in amd_gpio_probe()
955 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), in amd_gpio_probe()
956 0, 0, gpio_dev->gc.ngpio); in amd_gpio_probe()
958 dev_err(&pdev->dev, "Failed to add pin range\n"); in amd_gpio_probe()
962 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, in amd_gpio_probe()
969 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); in amd_gpio_probe()
973 gpiochip_remove(&gpio_dev->gc); in amd_gpio_probe()
984 gpiochip_remove(&gpio_dev->gc); in amd_gpio_remove()