Lines Matching +full:gpo +full:- +full:config +full:-
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2016-2018 Nuvoton Technology corporation.
16 #include <linux/pinctrl/pinconf-generic.h>
47 #define NPCM7XX_GP_N_PU 0x1c /* Pull-up */
48 #define NPCM7XX_GP_N_PD 0x20 /* Pull-down */
107 spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_set()
112 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_set()
121 spin_lock_irqsave(&gc->bgpio_lock, flags); in npcm_gpio_clr()
126 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in npcm_gpio_clr()
133 seq_printf(s, "-- module %d [gpio%d - %d]\n", in npcmgpio_dbg_show()
134 bank->gc.base / bank->gc.ngpio, in npcmgpio_dbg_show()
135 bank->gc.base, in npcmgpio_dbg_show()
136 bank->gc.base + bank->gc.ngpio); in npcmgpio_dbg_show()
138 ioread32(bank->base + NPCM7XX_GP_N_DIN), in npcmgpio_dbg_show()
139 ioread32(bank->base + NPCM7XX_GP_N_DOUT), in npcmgpio_dbg_show()
140 ioread32(bank->base + NPCM7XX_GP_N_IEM), in npcmgpio_dbg_show()
141 ioread32(bank->base + NPCM7XX_GP_N_OE)); in npcmgpio_dbg_show()
143 ioread32(bank->base + NPCM7XX_GP_N_PU), in npcmgpio_dbg_show()
144 ioread32(bank->base + NPCM7XX_GP_N_PD), in npcmgpio_dbg_show()
145 ioread32(bank->base + NPCM7XX_GP_N_DBNC), in npcmgpio_dbg_show()
146 ioread32(bank->base + NPCM7XX_GP_N_POL)); in npcmgpio_dbg_show()
148 ioread32(bank->base + NPCM7XX_GP_N_EVTYP), in npcmgpio_dbg_show()
149 ioread32(bank->base + NPCM7XX_GP_N_EVBE), in npcmgpio_dbg_show()
150 ioread32(bank->base + NPCM7XX_GP_N_EVEN), in npcmgpio_dbg_show()
151 ioread32(bank->base + NPCM7XX_GP_N_EVST)); in npcmgpio_dbg_show()
153 ioread32(bank->base + NPCM7XX_GP_N_OTYP), in npcmgpio_dbg_show()
154 ioread32(bank->base + NPCM7XX_GP_N_OSRC), in npcmgpio_dbg_show()
155 ioread32(bank->base + NPCM7XX_GP_N_ODSC)); in npcmgpio_dbg_show()
157 ioread32(bank->base + NPCM7XX_GP_N_OBL0), in npcmgpio_dbg_show()
158 ioread32(bank->base + NPCM7XX_GP_N_OBL1), in npcmgpio_dbg_show()
159 ioread32(bank->base + NPCM7XX_GP_N_OBL2), in npcmgpio_dbg_show()
160 ioread32(bank->base + NPCM7XX_GP_N_OBL3)); in npcmgpio_dbg_show()
162 ioread32(bank->base + NPCM7XX_GP_N_SPLCK), in npcmgpio_dbg_show()
163 ioread32(bank->base + NPCM7XX_GP_N_MPLCK)); in npcmgpio_dbg_show()
171 ret = pinctrl_gpio_direction_input(offset + chip->base); in npcmgpio_direction_input()
175 return bank->direction_input(chip, offset); in npcmgpio_direction_input()
185 dev_dbg(chip->parent, "gpio_direction_output: offset%d = %x\n", offset, in npcmgpio_direction_output()
188 ret = pinctrl_gpio_direction_output(offset + chip->base); in npcmgpio_direction_output()
192 return bank->direction_output(chip, offset, value); in npcmgpio_direction_output()
200 dev_dbg(chip->parent, "gpio_request: offset%d\n", offset); in npcmgpio_gpio_request()
201 ret = pinctrl_gpio_request(offset + chip->base); in npcmgpio_gpio_request()
205 return bank->request(chip, offset); in npcmgpio_gpio_request()
210 dev_dbg(chip->parent, "gpio_free: offset%d\n", offset); in npcmgpio_gpio_free()
211 pinctrl_gpio_free(offset + chip->base); in npcmgpio_gpio_free()
226 sts = ioread32(bank->base + NPCM7XX_GP_N_EVST); in npcmgpio_irq_handler()
227 en = ioread32(bank->base + NPCM7XX_GP_N_EVEN); in npcmgpio_irq_handler()
228 dev_dbg(bank->gc.parent, "==> got irq sts %.8x %.8x\n", sts, in npcmgpio_irq_handler()
233 generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit)); in npcmgpio_irq_handler()
241 unsigned int gpio = BIT(d->hwirq); in npcmgpio_set_irq_type()
243 dev_dbg(bank->gc.parent, "setirqtype: %u.%u = %u\n", gpio, in npcmgpio_set_irq_type()
244 d->irq, type); in npcmgpio_set_irq_type()
247 dev_dbg(bank->gc.parent, "edge.rising\n"); in npcmgpio_set_irq_type()
248 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
249 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
252 dev_dbg(bank->gc.parent, "edge.falling\n"); in npcmgpio_set_irq_type()
253 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
254 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
257 dev_dbg(bank->gc.parent, "edge.both\n"); in npcmgpio_set_irq_type()
258 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio); in npcmgpio_set_irq_type()
261 dev_dbg(bank->gc.parent, "level.low\n"); in npcmgpio_set_irq_type()
262 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
265 dev_dbg(bank->gc.parent, "level.high\n"); in npcmgpio_set_irq_type()
266 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio); in npcmgpio_set_irq_type()
269 dev_dbg(bank->gc.parent, "invalid irq type\n"); in npcmgpio_set_irq_type()
270 return -EINVAL; in npcmgpio_set_irq_type()
274 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); in npcmgpio_set_irq_type()
278 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio); in npcmgpio_set_irq_type()
289 unsigned int gpio = d->hwirq; in npcmgpio_irq_ack()
291 dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq); in npcmgpio_irq_ack()
292 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST); in npcmgpio_irq_ack()
300 unsigned int gpio = d->hwirq; in npcmgpio_irq_mask()
303 dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq); in npcmgpio_irq_mask()
304 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC); in npcmgpio_irq_mask()
312 unsigned int gpio = d->hwirq; in npcmgpio_irq_unmask()
315 dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq); in npcmgpio_irq_unmask()
316 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS); in npcmgpio_irq_unmask()
322 unsigned int gpio = d->hwirq; in npcmgpio_irq_startup()
324 /* active-high, input, clear interrupt, enable interrupt */ in npcmgpio_irq_startup()
325 dev_dbg(gc->parent, "startup: %u.%u\n", gpio, d->irq); in npcmgpio_irq_startup()
334 .name = "NPCM7XX-GPIO-IRQ",
912 #define GPI 0x1 /* Not GPO */
913 #define GPO 0x2 /* Not GPI */ macro
967 …7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO),
973 NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO),
976 NPCM7XX_PINCFG(51, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
978 NPCM7XX_PINCFG(53, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
986 NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO),
987 NPCM7XX_PINCFG(62, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
988 NPCM7XX_PINCFG(63, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
1113 …X_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
1114 …X_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
1156 …PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
1157 …PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO),
1419 if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) { in npcm7xx_setfunc()
1420 if (cfg->reg0) in npcm7xx_setfunc()
1421 regmap_update_bits(gcr_regmap, cfg->reg0, in npcm7xx_setfunc()
1422 BIT(cfg->bit0), in npcm7xx_setfunc()
1423 !!(cfg->fn0 == mode) ? in npcm7xx_setfunc()
1424 BIT(cfg->bit0) : 0); in npcm7xx_setfunc()
1425 if (cfg->reg1) in npcm7xx_setfunc()
1426 regmap_update_bits(gcr_regmap, cfg->reg1, in npcm7xx_setfunc()
1427 BIT(cfg->bit1), in npcm7xx_setfunc()
1428 !!(cfg->fn1 == mode) ? in npcm7xx_setfunc()
1429 BIT(cfg->bit1) : 0); in npcm7xx_setfunc()
1430 if (cfg->reg2) in npcm7xx_setfunc()
1431 regmap_update_bits(gcr_regmap, cfg->reg2, in npcm7xx_setfunc()
1432 BIT(cfg->bit2), in npcm7xx_setfunc()
1433 !!(cfg->fn2 == mode) ? in npcm7xx_setfunc()
1434 BIT(cfg->bit2) : 0); in npcm7xx_setfunc()
1444 int gpio = (pin % bank->gc.ngpio); in npcm7xx_get_slew_rate()
1448 return ioread32(bank->base + NPCM7XX_GP_N_OSRC) in npcm7xx_get_slew_rate()
1456 return -EINVAL; in npcm7xx_get_slew_rate()
1464 int gpio = BIT(pin % bank->gc.ngpio); in npcm7xx_set_slew_rate()
1469 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, in npcm7xx_set_slew_rate()
1473 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC, in npcm7xx_set_slew_rate()
1477 return -EINVAL; in npcm7xx_set_slew_rate()
1492 return -EINVAL; in npcm7xx_set_slew_rate()
1496 return -EINVAL; in npcm7xx_set_slew_rate()
1505 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; in npcm7xx_get_drive_strength()
1506 int gpio = (pin % bank->gc.ngpio); in npcm7xx_get_drive_strength()
1514 val = ioread32(bank->base + NPCM7XX_GP_N_ODSC) in npcm7xx_get_drive_strength()
1517 dev_dbg(bank->gc.parent, in npcm7xx_get_drive_strength()
1522 return -EINVAL; in npcm7xx_get_drive_strength()
1531 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; in npcm7xx_set_drive_strength()
1532 int gpio = BIT(pin % bank->gc.ngpio); in npcm7xx_set_drive_strength()
1536 return -ENOTSUPP; in npcm7xx_set_drive_strength()
1538 dev_dbg(bank->gc.parent, in npcm7xx_set_drive_strength()
1540 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); in npcm7xx_set_drive_strength()
1543 dev_dbg(bank->gc.parent, in npcm7xx_set_drive_strength()
1545 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio); in npcm7xx_set_drive_strength()
1549 return -ENOTSUPP; in npcm7xx_set_drive_strength()
1563 dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups)); in npcm7xx_get_groups_count()
1591 dev_dbg(npcm->dev, "dt_node_to_map: %s\n", np_config->name); in npcm7xx_dt_node_to_map()
1641 dev_dbg(npcm->dev, "set_mux: %d, %d[%s]\n", function, group, in npcm7xx_pinmux_set_mux()
1644 npcm7xx_setfunc(npcm->gcr_regmap, npcm7xx_groups[group].pins, in npcm7xx_pinmux_set_mux()
1657 dev_err(npcm->dev, "invalid range\n"); in npcm7xx_gpio_request_enable()
1658 return -EINVAL; in npcm7xx_gpio_request_enable()
1660 if (!range->gc) { in npcm7xx_gpio_request_enable()
1661 dev_err(npcm->dev, "invalid gpiochip\n"); in npcm7xx_gpio_request_enable()
1662 return -EINVAL; in npcm7xx_gpio_request_enable()
1665 npcm7xx_setfunc(npcm->gcr_regmap, &offset, 1, fn_gpio); in npcm7xx_gpio_request_enable()
1678 virq = irq_find_mapping(npcm->domain, offset); in npcm7xx_gpio_request_free()
1690 &npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK]; in npcm_gpio_set_direction()
1691 int gpio = BIT(offset % bank->gc.ngpio); in npcm_gpio_set_direction()
1693 dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset, in npcm_gpio_set_direction()
1696 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); in npcm_gpio_set_direction()
1698 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); in npcm_gpio_set_direction()
1715 unsigned long *config) in npcm7xx_config_get() argument
1717 enum pin_config_param param = pinconf_to_config_param(*config); in npcm7xx_config_get()
1720 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; in npcm7xx_config_get()
1721 int gpio = (pin % bank->gc.ngpio); in npcm7xx_config_get()
1730 pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask; in npcm7xx_config_get()
1731 pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask; in npcm7xx_config_get()
1741 ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask; in npcm7xx_config_get()
1742 oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask; in npcm7xx_config_get()
1749 rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask); in npcm7xx_config_get()
1752 rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask; in npcm7xx_config_get()
1755 rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask; in npcm7xx_config_get()
1760 *config = pinconf_to_config_packed(param, rc); in npcm7xx_config_get()
1763 rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin); in npcm7xx_config_get()
1765 *config = pinconf_to_config_packed(param, rc); in npcm7xx_config_get()
1768 return -ENOTSUPP; in npcm7xx_config_get()
1772 return -EINVAL; in npcm7xx_config_get()
1778 unsigned int pin, unsigned long config) in npcm7xx_config_set_one() argument
1780 enum pin_config_param param = pinconf_to_config_param(config); in npcm7xx_config_set_one()
1781 u16 arg = pinconf_to_config_argument(config); in npcm7xx_config_set_one()
1783 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; in npcm7xx_config_set_one()
1784 int gpio = BIT(pin % bank->gc.ngpio); in npcm7xx_config_set_one()
1786 dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin); in npcm7xx_config_set_one()
1789 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); in npcm7xx_config_set_one()
1790 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); in npcm7xx_config_set_one()
1793 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); in npcm7xx_config_set_one()
1794 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); in npcm7xx_config_set_one()
1797 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio); in npcm7xx_config_set_one()
1798 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio); in npcm7xx_config_set_one()
1801 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); in npcm7xx_config_set_one()
1802 bank->direction_input(&bank->gc, pin % bank->gc.ngpio); in npcm7xx_config_set_one()
1805 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); in npcm7xx_config_set_one()
1806 bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); in npcm7xx_config_set_one()
1809 npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); in npcm7xx_config_set_one()
1812 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio); in npcm7xx_config_set_one()
1815 npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio); in npcm7xx_config_set_one()
1818 return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg); in npcm7xx_config_set_one()
1822 return -ENOTSUPP; in npcm7xx_config_set_one()
1835 while (num_configs--) { in npcm7xx_config_set()
1852 .name = "npcm7xx-pinctrl",
1863 int ret = -ENXIO; in npcm7xx_gpio_of()
1869 for_each_available_child_of_node(pctrl->dev->of_node, np) in npcm7xx_gpio_of()
1870 if (of_find_property(np, "gpio-controller", NULL)) { in npcm7xx_gpio_of()
1873 dev_err(pctrl->dev, in npcm7xx_gpio_of()
1878 pctrl->gpio_bank[id].base = in npcm7xx_gpio_of()
1883 dev_err(pctrl->dev, in npcm7xx_gpio_of()
1889 ret = bgpio_init(&pctrl->gpio_bank[id].gc, in npcm7xx_gpio_of()
1890 pctrl->dev, 4, in npcm7xx_gpio_of()
1891 pctrl->gpio_bank[id].base + in npcm7xx_gpio_of()
1893 pctrl->gpio_bank[id].base + in npcm7xx_gpio_of()
1897 pctrl->gpio_bank[id].base + in npcm7xx_gpio_of()
1901 dev_err(pctrl->dev, "bgpio_init() failed\n"); in npcm7xx_gpio_of()
1906 "gpio-ranges", 3, in npcm7xx_gpio_of()
1909 dev_err(pctrl->dev, in npcm7xx_gpio_of()
1910 "gpio-ranges fail for GPIO bank %u\n", in npcm7xx_gpio_of()
1915 pctrl->gpio_bank[id].irq = irq; in npcm7xx_gpio_of()
1916 pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip; in npcm7xx_gpio_of()
1917 pctrl->gpio_bank[id].gc.parent = pctrl->dev; in npcm7xx_gpio_of()
1918 pctrl->gpio_bank[id].irqbase = in npcm7xx_gpio_of()
1920 pctrl->gpio_bank[id].pinctrl_id = pinspec.args[0]; in npcm7xx_gpio_of()
1921 pctrl->gpio_bank[id].gc.base = pinspec.args[1]; in npcm7xx_gpio_of()
1922 pctrl->gpio_bank[id].gc.ngpio = pinspec.args[2]; in npcm7xx_gpio_of()
1923 pctrl->gpio_bank[id].gc.owner = THIS_MODULE; in npcm7xx_gpio_of()
1924 pctrl->gpio_bank[id].gc.label = in npcm7xx_gpio_of()
1925 devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOF", in npcm7xx_gpio_of()
1927 if (pctrl->gpio_bank[id].gc.label == NULL) in npcm7xx_gpio_of()
1928 return -ENOMEM; in npcm7xx_gpio_of()
1930 pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show; in npcm7xx_gpio_of()
1931 pctrl->gpio_bank[id].direction_input = in npcm7xx_gpio_of()
1932 pctrl->gpio_bank[id].gc.direction_input; in npcm7xx_gpio_of()
1933 pctrl->gpio_bank[id].gc.direction_input = in npcm7xx_gpio_of()
1935 pctrl->gpio_bank[id].direction_output = in npcm7xx_gpio_of()
1936 pctrl->gpio_bank[id].gc.direction_output; in npcm7xx_gpio_of()
1937 pctrl->gpio_bank[id].gc.direction_output = in npcm7xx_gpio_of()
1939 pctrl->gpio_bank[id].request = in npcm7xx_gpio_of()
1940 pctrl->gpio_bank[id].gc.request; in npcm7xx_gpio_of()
1941 pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request; in npcm7xx_gpio_of()
1942 pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free; in npcm7xx_gpio_of()
1943 pctrl->gpio_bank[id].gc.of_node = np; in npcm7xx_gpio_of()
1947 pctrl->bank_num = id; in npcm7xx_gpio_of()
1955 for (id = 0 ; id < pctrl->bank_num ; id++) { in npcm7xx_gpio_register()
1958 girq = &pctrl->gpio_bank[id].gc.irq; in npcm7xx_gpio_register()
1959 girq->chip = &pctrl->gpio_bank[id].irq_chip; in npcm7xx_gpio_register()
1960 girq->parent_handler = npcmgpio_irq_handler; in npcm7xx_gpio_register()
1961 girq->num_parents = 1; in npcm7xx_gpio_register()
1962 girq->parents = devm_kcalloc(pctrl->dev, 1, in npcm7xx_gpio_register()
1963 sizeof(*girq->parents), in npcm7xx_gpio_register()
1965 if (!girq->parents) { in npcm7xx_gpio_register()
1966 ret = -ENOMEM; in npcm7xx_gpio_register()
1969 girq->parents[0] = pctrl->gpio_bank[id].irq; in npcm7xx_gpio_register()
1970 girq->default_type = IRQ_TYPE_NONE; in npcm7xx_gpio_register()
1971 girq->handler = handle_level_irq; in npcm7xx_gpio_register()
1972 ret = devm_gpiochip_add_data(pctrl->dev, in npcm7xx_gpio_register()
1973 &pctrl->gpio_bank[id].gc, in npcm7xx_gpio_register()
1974 &pctrl->gpio_bank[id]); in npcm7xx_gpio_register()
1976 dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id); in npcm7xx_gpio_register()
1980 ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].gc, in npcm7xx_gpio_register()
1981 dev_name(pctrl->dev), in npcm7xx_gpio_register()
1982 pctrl->gpio_bank[id].pinctrl_id, in npcm7xx_gpio_register()
1983 pctrl->gpio_bank[id].gc.base, in npcm7xx_gpio_register()
1984 pctrl->gpio_bank[id].gc.ngpio); in npcm7xx_gpio_register()
1986 dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id); in npcm7xx_gpio_register()
1987 gpiochip_remove(&pctrl->gpio_bank[id].gc); in npcm7xx_gpio_register()
1995 for (; id > 0; id--) in npcm7xx_gpio_register()
1996 gpiochip_remove(&pctrl->gpio_bank[id - 1].gc); in npcm7xx_gpio_register()
2006 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in npcm7xx_pinctrl_probe()
2008 return -ENOMEM; in npcm7xx_pinctrl_probe()
2010 pctrl->dev = &pdev->dev; in npcm7xx_pinctrl_probe()
2011 dev_set_drvdata(&pdev->dev, pctrl); in npcm7xx_pinctrl_probe()
2013 pctrl->gcr_regmap = in npcm7xx_pinctrl_probe()
2014 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); in npcm7xx_pinctrl_probe()
2015 if (IS_ERR(pctrl->gcr_regmap)) { in npcm7xx_pinctrl_probe()
2016 dev_err(pctrl->dev, "didn't find nuvoton,npcm750-gcr\n"); in npcm7xx_pinctrl_probe()
2017 return PTR_ERR(pctrl->gcr_regmap); in npcm7xx_pinctrl_probe()
2022 dev_err(pctrl->dev, "Failed to gpio dt-binding %u\n", ret); in npcm7xx_pinctrl_probe()
2026 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, in npcm7xx_pinctrl_probe()
2028 if (IS_ERR(pctrl->pctldev)) { in npcm7xx_pinctrl_probe()
2029 dev_err(&pdev->dev, "Failed to register pinctrl device\n"); in npcm7xx_pinctrl_probe()
2030 return PTR_ERR(pctrl->pctldev); in npcm7xx_pinctrl_probe()
2035 dev_err(pctrl->dev, "Failed to register gpio %u\n", ret); in npcm7xx_pinctrl_probe()
2044 { .compatible = "nuvoton,npcm750-pinctrl" },
2052 .name = "npcm7xx-pinctrl",