286 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_mode()  argument
291 	afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);  in __nmk_gpio_set_mode()
292 	bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);  in __nmk_gpio_set_mode()
297 	writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);  in __nmk_gpio_set_mode()
298 	writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);  in __nmk_gpio_set_mode()
301 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_slpm()  argument
306 	slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);  in __nmk_gpio_set_slpm()
311 	writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);  in __nmk_gpio_set_slpm()
314 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_pull()  argument
319 	pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);  in __nmk_gpio_set_pull()
322 		nmk_chip->pull_up &= ~BIT(offset);  in __nmk_gpio_set_pull()
327 	writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);  in __nmk_gpio_set_pull()
330 		nmk_chip->pull_up |= BIT(offset);  in __nmk_gpio_set_pull()
331 		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);  in __nmk_gpio_set_pull()
333 		nmk_chip->pull_up &= ~BIT(offset);  in __nmk_gpio_set_pull()
334 		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);  in __nmk_gpio_set_pull()
338 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_lowemi()  argument
341 	bool enabled = nmk_chip->lowemi & BIT(offset);  in __nmk_gpio_set_lowemi()
347 		nmk_chip->lowemi |= BIT(offset);  in __nmk_gpio_set_lowemi()
349 		nmk_chip->lowemi &= ~BIT(offset);  in __nmk_gpio_set_lowemi()
351 	writel_relaxed(nmk_chip->lowemi,  in __nmk_gpio_set_lowemi()
352 		       nmk_chip->addr + NMK_GPIO_LOWEMI);  in __nmk_gpio_set_lowemi()
355 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_make_input()  argument
358 	writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);  in __nmk_gpio_make_input()
361 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_output()  argument
365 		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);  in __nmk_gpio_set_output()
367 		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);  in __nmk_gpio_set_output()
370 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_make_output()  argument
373 	writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);  in __nmk_gpio_make_output()
374 	__nmk_gpio_set_output(nmk_chip, offset, val);  in __nmk_gpio_make_output()
377 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_mode_safe()  argument
381 	u32 rwimsc = nmk_chip->rwimsc;  in __nmk_gpio_set_mode_safe()
382 	u32 fwimsc = nmk_chip->fwimsc;  in __nmk_gpio_set_mode_safe()
384 	if (glitch && nmk_chip->set_ioforce) {  in __nmk_gpio_set_mode_safe()
388 		writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);  in __nmk_gpio_set_mode_safe()
389 		writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);  in __nmk_gpio_set_mode_safe()
391 		nmk_chip->set_ioforce(true);  in __nmk_gpio_set_mode_safe()
394 	__nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);  in __nmk_gpio_set_mode_safe()
396 	if (glitch && nmk_chip->set_ioforce) {  in __nmk_gpio_set_mode_safe()
397 		nmk_chip->set_ioforce(false);  in __nmk_gpio_set_mode_safe()
399 		writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);  in __nmk_gpio_set_mode_safe()
400 		writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);  in __nmk_gpio_set_mode_safe()
405 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)  in nmk_gpio_disable_lazy_irq()  argument
407 	u32 falling = nmk_chip->fimsc & BIT(offset);  in nmk_gpio_disable_lazy_irq()
408 	u32 rising = nmk_chip->rimsc & BIT(offset);  in nmk_gpio_disable_lazy_irq()
409 	int gpio = nmk_chip->chip.base + offset;  in nmk_gpio_disable_lazy_irq()
410 	int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);  in nmk_gpio_disable_lazy_irq()
420 		nmk_chip->rimsc &= ~BIT(offset);  in nmk_gpio_disable_lazy_irq()
421 		writel_relaxed(nmk_chip->rimsc,  in nmk_gpio_disable_lazy_irq()
422 			       nmk_chip->addr + NMK_GPIO_RIMSC);  in nmk_gpio_disable_lazy_irq()
426 		nmk_chip->fimsc &= ~BIT(offset);  in nmk_gpio_disable_lazy_irq()
427 		writel_relaxed(nmk_chip->fimsc,  in nmk_gpio_disable_lazy_irq()
428 			       nmk_chip->addr + NMK_GPIO_FIMSC);  in nmk_gpio_disable_lazy_irq()
431 	dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);  in nmk_gpio_disable_lazy_irq()
612 	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);  in nmk_gpio_irq_ack()  local
614 	clk_enable(nmk_chip->clk);  in nmk_gpio_irq_ack()
615 	writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);  in nmk_gpio_irq_ack()
616 	clk_disable(nmk_chip->clk);  in nmk_gpio_irq_ack()
624 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_irq_modify()  argument
636 		rimscval = &nmk_chip->rimsc;  in __nmk_gpio_irq_modify()
637 		fimscval = &nmk_chip->fimsc;  in __nmk_gpio_irq_modify()
641 		rimscval = &nmk_chip->rwimsc;  in __nmk_gpio_irq_modify()
642 		fimscval = &nmk_chip->fwimsc;  in __nmk_gpio_irq_modify()
646 	if (nmk_chip->edge_rising & BIT(offset)) {  in __nmk_gpio_irq_modify()
651 		writel(*rimscval, nmk_chip->addr + rimscreg);  in __nmk_gpio_irq_modify()
653 	if (nmk_chip->edge_falling & BIT(offset)) {  in __nmk_gpio_irq_modify()
658 		writel(*fimscval, nmk_chip->addr + fimscreg);  in __nmk_gpio_irq_modify()
662 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,  in __nmk_gpio_set_wake()  argument
670 	if (nmk_chip->sleepmode && on) {  in __nmk_gpio_set_wake()
671 		__nmk_gpio_set_slpm(nmk_chip, offset,  in __nmk_gpio_set_wake()
675 	__nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);  in __nmk_gpio_set_wake()
680 	struct nmk_gpio_chip *nmk_chip;  in nmk_gpio_irq_maskunmask()  local
683 	nmk_chip = irq_data_get_irq_chip_data(d);  in nmk_gpio_irq_maskunmask()
684 	if (!nmk_chip)  in nmk_gpio_irq_maskunmask()
687 	clk_enable(nmk_chip->clk);  in nmk_gpio_irq_maskunmask()
689 	spin_lock(&nmk_chip->lock);  in nmk_gpio_irq_maskunmask()
691 	__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);  in nmk_gpio_irq_maskunmask()
693 	if (!(nmk_chip->real_wake & BIT(d->hwirq)))  in nmk_gpio_irq_maskunmask()
694 		__nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);  in nmk_gpio_irq_maskunmask()
696 	spin_unlock(&nmk_chip->lock);  in nmk_gpio_irq_maskunmask()
698 	clk_disable(nmk_chip->clk);  in nmk_gpio_irq_maskunmask()
715 	struct nmk_gpio_chip *nmk_chip;  in nmk_gpio_irq_set_wake()  local
718 	nmk_chip = irq_data_get_irq_chip_data(d);  in nmk_gpio_irq_set_wake()
719 	if (!nmk_chip)  in nmk_gpio_irq_set_wake()
722 	clk_enable(nmk_chip->clk);  in nmk_gpio_irq_set_wake()
724 	spin_lock(&nmk_chip->lock);  in nmk_gpio_irq_set_wake()
727 		__nmk_gpio_set_wake(nmk_chip, d->hwirq, on);  in nmk_gpio_irq_set_wake()
730 		nmk_chip->real_wake |= BIT(d->hwirq);  in nmk_gpio_irq_set_wake()
732 		nmk_chip->real_wake &= ~BIT(d->hwirq);  in nmk_gpio_irq_set_wake()
734 	spin_unlock(&nmk_chip->lock);  in nmk_gpio_irq_set_wake()
736 	clk_disable(nmk_chip->clk);  in nmk_gpio_irq_set_wake()
745 	struct nmk_gpio_chip *nmk_chip;  in nmk_gpio_irq_set_type()  local
748 	nmk_chip = irq_data_get_irq_chip_data(d);  in nmk_gpio_irq_set_type()
749 	if (!nmk_chip)  in nmk_gpio_irq_set_type()
756 	clk_enable(nmk_chip->clk);  in nmk_gpio_irq_set_type()
757 	spin_lock_irqsave(&nmk_chip->lock, flags);  in nmk_gpio_irq_set_type()
760 		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);  in nmk_gpio_irq_set_type()
763 		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);  in nmk_gpio_irq_set_type()
765 	nmk_chip->edge_rising &= ~BIT(d->hwirq);  in nmk_gpio_irq_set_type()
767 		nmk_chip->edge_rising |= BIT(d->hwirq);  in nmk_gpio_irq_set_type()
769 	nmk_chip->edge_falling &= ~BIT(d->hwirq);  in nmk_gpio_irq_set_type()
771 		nmk_chip->edge_falling |= BIT(d->hwirq);  in nmk_gpio_irq_set_type()
774 		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);  in nmk_gpio_irq_set_type()
777 		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);  in nmk_gpio_irq_set_type()
779 	spin_unlock_irqrestore(&nmk_chip->lock, flags);  in nmk_gpio_irq_set_type()
780 	clk_disable(nmk_chip->clk);  in nmk_gpio_irq_set_type()
787 	struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);  in nmk_gpio_irq_startup()  local
789 	clk_enable(nmk_chip->clk);  in nmk_gpio_irq_startup()
796 	struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);  in nmk_gpio_irq_shutdown()  local
799 	clk_disable(nmk_chip->clk);  in nmk_gpio_irq_shutdown()
806 	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);  in nmk_gpio_irq_handler()  local
811 	clk_enable(nmk_chip->clk);  in nmk_gpio_irq_handler()
812 	status = readl(nmk_chip->addr + NMK_GPIO_IS);  in nmk_gpio_irq_handler()
813 	clk_disable(nmk_chip->clk);  in nmk_gpio_irq_handler()
829 	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);  in nmk_gpio_get_dir()  local
832 	clk_enable(nmk_chip->clk);  in nmk_gpio_get_dir()
834 	dir = readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset);  in nmk_gpio_get_dir()
836 	clk_disable(nmk_chip->clk);  in nmk_gpio_get_dir()
846 	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);  in nmk_gpio_make_input()  local
848 	clk_enable(nmk_chip->clk);  in nmk_gpio_make_input()
850 	writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);  in nmk_gpio_make_input()
852 	clk_disable(nmk_chip->clk);  in nmk_gpio_make_input()
859 	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);  in nmk_gpio_get_input()  local
862 	clk_enable(nmk_chip->clk);  in nmk_gpio_get_input()
864 	value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));  in nmk_gpio_get_input()
866 	clk_disable(nmk_chip->clk);  in nmk_gpio_get_input()
874 	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);  in nmk_gpio_set_output()  local
876 	clk_enable(nmk_chip->clk);  in nmk_gpio_set_output()
878 	__nmk_gpio_set_output(nmk_chip, offset, val);  in nmk_gpio_set_output()
880 	clk_disable(nmk_chip->clk);  in nmk_gpio_set_output()
886 	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);  in nmk_gpio_make_output()  local
888 	clk_enable(nmk_chip->clk);  in nmk_gpio_make_output()
890 	__nmk_gpio_make_output(nmk_chip, offset, val);  in nmk_gpio_make_output()
892 	clk_disable(nmk_chip->clk);  in nmk_gpio_make_output()
898 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)  in nmk_gpio_get_mode()  argument
902 	clk_enable(nmk_chip->clk);  in nmk_gpio_get_mode()
904 	afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);  in nmk_gpio_get_mode()
905 	bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);  in nmk_gpio_get_mode()
907 	clk_disable(nmk_chip->clk);  in nmk_gpio_get_mode()
919 	struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);  in nmk_gpio_dbg_show_one()  local
935 	clk_enable(nmk_chip->clk);  in nmk_gpio_dbg_show_one()
936 	is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));  in nmk_gpio_dbg_show_one()
937 	pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));  in nmk_gpio_dbg_show_one()
938 	data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));  in nmk_gpio_dbg_show_one()
939 	mode = nmk_gpio_get_mode(nmk_chip, offset);  in nmk_gpio_dbg_show_one()
975 			if (nmk_chip->edge_rising & BIT(offset))  in nmk_gpio_dbg_show_one()
977 			else if (nmk_chip->edge_falling & BIT(offset))  in nmk_gpio_dbg_show_one()
988 	clk_disable(nmk_chip->clk);  in nmk_gpio_dbg_show_one()
1021 	struct nmk_gpio_chip *nmk_chip;  in nmk_gpio_populate_chip()  local
1041 	nmk_chip = nmk_gpio_chips[id];  in nmk_gpio_populate_chip()
1042 	if (nmk_chip) {  in nmk_gpio_populate_chip()
1044 		return nmk_chip;  in nmk_gpio_populate_chip()
1047 	nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);  in nmk_gpio_populate_chip()
1048 	if (!nmk_chip) {  in nmk_gpio_populate_chip()
1053 	nmk_chip->bank = id;  in nmk_gpio_populate_chip()
1054 	chip = &nmk_chip->chip;  in nmk_gpio_populate_chip()
1066 	nmk_chip->addr = base;  in nmk_gpio_populate_chip()
1074 	nmk_chip->clk = clk;  in nmk_gpio_populate_chip()
1076 	BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));  in nmk_gpio_populate_chip()
1077 	nmk_gpio_chips[id] = nmk_chip;  in nmk_gpio_populate_chip()
1078 	return nmk_chip;  in nmk_gpio_populate_chip()
1084 	struct nmk_gpio_chip *nmk_chip;  in nmk_gpio_probe()  local
1092 	nmk_chip = nmk_gpio_populate_chip(np, dev);  in nmk_gpio_probe()
1093 	if (IS_ERR(nmk_chip)) {  in nmk_gpio_probe()
1095 		return PTR_ERR(nmk_chip);  in nmk_gpio_probe()
1102 	dev->id = nmk_chip->bank;  in nmk_gpio_probe()
1112 	nmk_chip->sleepmode = supports_sleepmode;  in nmk_gpio_probe()
1113 	spin_lock_init(&nmk_chip->lock);  in nmk_gpio_probe()
1115 	chip = &nmk_chip->chip;  in nmk_gpio_probe()
1127 	irqchip = &nmk_chip->irqchip;  in nmk_gpio_probe()
1154 	clk_enable(nmk_chip->clk);  in nmk_gpio_probe()
1155 	nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);  in nmk_gpio_probe()
1156 	clk_disable(nmk_chip->clk);  in nmk_gpio_probe()
1159 	ret = gpiochip_add_data(chip, nmk_chip);  in nmk_gpio_probe()
1163 	platform_set_drvdata(dev, nmk_chip);  in nmk_gpio_probe()
1575 		struct nmk_gpio_chip *nmk_chip;  in nmk_pmx_set()  local
1578 		nmk_chip = find_nmk_gpio_from_pin(g->pins[i]);  in nmk_pmx_set()
1579 		if (!nmk_chip) {  in nmk_pmx_set()
1587 		clk_enable(nmk_chip->clk);  in nmk_pmx_set()
1596 		nmk_gpio_disable_lazy_irq(nmk_chip, bit);  in nmk_pmx_set()
1598 		__nmk_gpio_set_mode_safe(nmk_chip, bit,  in nmk_pmx_set()
1600 		clk_disable(nmk_chip->clk);  in nmk_pmx_set()
1632 	struct nmk_gpio_chip *nmk_chip;  in nmk_gpio_request_enable()  local
1645 	nmk_chip = gpiochip_get_data(chip);  in nmk_gpio_request_enable()
1649 	clk_enable(nmk_chip->clk);  in nmk_gpio_request_enable()
1652 	__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);  in nmk_gpio_request_enable()
1653 	clk_disable(nmk_chip->clk);  in nmk_gpio_request_enable()
1699 	struct nmk_gpio_chip *nmk_chip;  in nmk_pin_config_set()  local
1705 	nmk_chip = find_nmk_gpio_from_pin(pin);  in nmk_pin_config_set()
1706 	if (!nmk_chip) {  in nmk_pin_config_set()
1746 			dev_dbg(nmk_chip->chip.parent,  in nmk_pin_config_set()
1755 		dev_dbg(nmk_chip->chip.parent,  in nmk_pin_config_set()
1762 		clk_enable(nmk_chip->clk);  in nmk_pin_config_set()
1766 			__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);  in nmk_pin_config_set()
1768 			__nmk_gpio_make_output(nmk_chip, bit, val);  in nmk_pin_config_set()
1770 			__nmk_gpio_make_input(nmk_chip, bit);  in nmk_pin_config_set()
1771 			__nmk_gpio_set_pull(nmk_chip, bit, pull);  in nmk_pin_config_set()
1774 		__nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);  in nmk_pin_config_set()
1776 		__nmk_gpio_set_slpm(nmk_chip, bit, slpm);  in nmk_pin_config_set()
1777 		clk_disable(nmk_chip->clk);  in nmk_pin_config_set()
1871 		struct nmk_gpio_chip *nmk_chip;  in nmk_pinctrl_probe()  local
1878 			nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);  in nmk_pinctrl_probe()
1879 			if (IS_ERR(nmk_chip))  in nmk_pinctrl_probe()