Lines Matching +full:pinctrl +full:- +full:1
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
28 #include "../pinctrl-utils.h"
106 * Northstar2 IOMUX pinctrl core
145 * @pull_shift: pull-up/pull-down control bit shift in the register
188 NS2_PIN_DESC(0, "mfio_0", -1, 0, 0, 0, 0, 0),
189 NS2_PIN_DESC(1, "mfio_1", -1, 0, 0, 0, 0, 0),
190 NS2_PIN_DESC(2, "mfio_2", -1, 0, 0, 0, 0, 0),
191 NS2_PIN_DESC(3, "mfio_3", -1, 0, 0, 0, 0, 0),
192 NS2_PIN_DESC(4, "mfio_4", -1, 0, 0, 0, 0, 0),
193 NS2_PIN_DESC(5, "mfio_5", -1, 0, 0, 0, 0, 0),
194 NS2_PIN_DESC(6, "mfio_6", -1, 0, 0, 0, 0, 0),
195 NS2_PIN_DESC(7, "mfio_7", -1, 0, 0, 0, 0, 0),
196 NS2_PIN_DESC(8, "mfio_8", -1, 0, 0, 0, 0, 0),
197 NS2_PIN_DESC(9, "mfio_9", -1, 0, 0, 0, 0, 0),
198 NS2_PIN_DESC(10, "mfio_10", -1, 0, 0, 0, 0, 0),
199 NS2_PIN_DESC(11, "mfio_11", -1, 0, 0, 0, 0, 0),
200 NS2_PIN_DESC(12, "mfio_12", -1, 0, 0, 0, 0, 0),
201 NS2_PIN_DESC(13, "mfio_13", -1, 0, 0, 0, 0, 0),
202 NS2_PIN_DESC(14, "mfio_14", -1, 0, 0, 0, 0, 0),
203 NS2_PIN_DESC(15, "mfio_15", -1, 0, 0, 0, 0, 0),
204 NS2_PIN_DESC(16, "mfio_16", -1, 0, 0, 0, 0, 0),
205 NS2_PIN_DESC(17, "mfio_17", -1, 0, 0, 0, 0, 0),
206 NS2_PIN_DESC(18, "mfio_18", -1, 0, 0, 0, 0, 0),
207 NS2_PIN_DESC(19, "mfio_19", -1, 0, 0, 0, 0, 0),
208 NS2_PIN_DESC(20, "mfio_20", -1, 0, 0, 0, 0, 0),
209 NS2_PIN_DESC(21, "mfio_21", -1, 0, 0, 0, 0, 0),
210 NS2_PIN_DESC(22, "mfio_22", -1, 0, 0, 0, 0, 0),
211 NS2_PIN_DESC(23, "mfio_23", -1, 0, 0, 0, 0, 0),
212 NS2_PIN_DESC(24, "mfio_24", -1, 0, 0, 0, 0, 0),
213 NS2_PIN_DESC(25, "mfio_25", -1, 0, 0, 0, 0, 0),
214 NS2_PIN_DESC(26, "mfio_26", -1, 0, 0, 0, 0, 0),
215 NS2_PIN_DESC(27, "mfio_27", -1, 0, 0, 0, 0, 0),
216 NS2_PIN_DESC(28, "mfio_28", -1, 0, 0, 0, 0, 0),
217 NS2_PIN_DESC(29, "mfio_29", -1, 0, 0, 0, 0, 0),
218 NS2_PIN_DESC(30, "mfio_30", -1, 0, 0, 0, 0, 0),
219 NS2_PIN_DESC(31, "mfio_31", -1, 0, 0, 0, 0, 0),
220 NS2_PIN_DESC(32, "mfio_32", -1, 0, 0, 0, 0, 0),
221 NS2_PIN_DESC(33, "mfio_33", -1, 0, 0, 0, 0, 0),
222 NS2_PIN_DESC(34, "mfio_34", -1, 0, 0, 0, 0, 0),
223 NS2_PIN_DESC(35, "mfio_35", -1, 0, 0, 0, 0, 0),
224 NS2_PIN_DESC(36, "mfio_36", -1, 0, 0, 0, 0, 0),
225 NS2_PIN_DESC(37, "mfio_37", -1, 0, 0, 0, 0, 0),
226 NS2_PIN_DESC(38, "mfio_38", -1, 0, 0, 0, 0, 0),
227 NS2_PIN_DESC(39, "mfio_39", -1, 0, 0, 0, 0, 0),
228 NS2_PIN_DESC(40, "mfio_40", -1, 0, 0, 0, 0, 0),
229 NS2_PIN_DESC(41, "mfio_41", -1, 0, 0, 0, 0, 0),
230 NS2_PIN_DESC(42, "mfio_42", -1, 0, 0, 0, 0, 0),
231 NS2_PIN_DESC(43, "mfio_43", -1, 0, 0, 0, 0, 0),
232 NS2_PIN_DESC(44, "mfio_44", -1, 0, 0, 0, 0, 0),
233 NS2_PIN_DESC(45, "mfio_45", -1, 0, 0, 0, 0, 0),
234 NS2_PIN_DESC(46, "mfio_46", -1, 0, 0, 0, 0, 0),
235 NS2_PIN_DESC(47, "mfio_47", -1, 0, 0, 0, 0, 0),
236 NS2_PIN_DESC(48, "mfio_48", -1, 0, 0, 0, 0, 0),
237 NS2_PIN_DESC(49, "mfio_49", -1, 0, 0, 0, 0, 0),
238 NS2_PIN_DESC(50, "mfio_50", -1, 0, 0, 0, 0, 0),
239 NS2_PIN_DESC(51, "mfio_51", -1, 0, 0, 0, 0, 0),
240 NS2_PIN_DESC(52, "mfio_52", -1, 0, 0, 0, 0, 0),
241 NS2_PIN_DESC(53, "mfio_53", -1, 0, 0, 0, 0, 0),
242 NS2_PIN_DESC(54, "mfio_54", -1, 0, 0, 0, 0, 0),
243 NS2_PIN_DESC(55, "mfio_55", -1, 0, 0, 0, 0, 0),
244 NS2_PIN_DESC(56, "mfio_56", -1, 0, 0, 0, 0, 0),
245 NS2_PIN_DESC(57, "mfio_57", -1, 0, 0, 0, 0, 0),
246 NS2_PIN_DESC(58, "mfio_58", -1, 0, 0, 0, 0, 0),
247 NS2_PIN_DESC(59, "mfio_59", -1, 0, 0, 0, 0, 0),
248 NS2_PIN_DESC(60, "mfio_60", -1, 0, 0, 0, 0, 0),
249 NS2_PIN_DESC(61, "mfio_61", -1, 0, 0, 0, 0, 0),
250 NS2_PIN_DESC(62, "mfio_62", -1, 0, 0, 0, 0, 0),
313 static const unsigned int nand_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
315 static const unsigned int nor_data_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
390 NS2_PIN_GROUP(nand, 0, 0, 31, 1, 0),
391 NS2_PIN_GROUP(nor_data, 0, 0, 31, 1, 1),
392 NS2_PIN_GROUP(gpio_0_1, 0, 0, 31, 1, 0),
394 NS2_PIN_GROUP(uart1_ext_clk, 0, 4, 30, 3, 1),
398 NS2_PIN_GROUP(pcie_ab1_clk_wak, 0, 4, 28, 3, 1),
402 NS2_PIN_GROUP(pcie_a3_clk_wak, 0, 4, 26, 3, 1),
406 NS2_PIN_GROUP(pcie_b3_clk_wak, 0, 4, 24, 3, 1),
410 NS2_PIN_GROUP(pcie_b2_clk_wak, 0, 4, 22, 3, 1),
414 NS2_PIN_GROUP(pcie_a2_clk_wak, 0, 4, 20, 3, 1),
418 NS2_PIN_GROUP(uart0_modem, 0, 4, 18, 3, 1),
422 NS2_PIN_GROUP(uart0_rts_cts, 0, 4, 16, 3, 1),
425 NS2_PIN_GROUP(uart0_in_out, 0, 4, 14, 3, 1),
428 NS2_PIN_GROUP(uart1_dcd_dsr, 0, 4, 12, 3, 1),
431 NS2_PIN_GROUP(uart1_ri_dtr, 0, 4, 10, 3, 1),
434 NS2_PIN_GROUP(uart1_rts_cts, 0, 4, 8, 3, 1),
437 NS2_PIN_GROUP(uart1_in_out, 0, 4, 6, 3, 1),
440 NS2_PIN_GROUP(uart2_rts_cts, 0, 4, 4, 3, 1),
442 NS2_PIN_GROUP(pwm_0, 1, 0, 0, 1, 1),
443 NS2_PIN_GROUP(pwm_1, 1, 0, 1, 1, 1),
444 NS2_PIN_GROUP(pwm_2, 1, 0, 2, 1, 1),
445 NS2_PIN_GROUP(pwm_3, 1, 0, 3, 1, 1),
503 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_get_groups_count() local
505 return pinctrl->num_groups; in ns2_get_groups_count()
511 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_get_group_name() local
513 return pinctrl->groups[selector].name; in ns2_get_group_name()
520 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_get_group_pins() local
522 *pins = pinctrl->groups[selector].pins; in ns2_get_group_pins()
523 *num_pins = pinctrl->groups[selector].num_pins; in ns2_get_group_pins()
531 seq_printf(s, " %s", dev_name(pctrl_dev->dev)); in ns2_pin_dbg_show()
545 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_get_functions_count() local
547 return pinctrl->num_functions; in ns2_get_functions_count()
553 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_get_function_name() local
555 return pinctrl->functions[selector].name; in ns2_get_function_name()
563 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_get_function_groups() local
565 *groups = pinctrl->functions[selector].groups; in ns2_get_function_groups()
566 *num_groups = pinctrl->functions[selector].num_groups; in ns2_get_function_groups()
571 static int ns2_pinmux_set(struct ns2_pinctrl *pinctrl, in ns2_pinmux_set() argument
576 const struct ns2_mux *mux = &grp->mux; in ns2_pinmux_set()
583 if ((mux->shift != mux_log[i].mux.shift) || in ns2_pinmux_set()
584 (mux->base != mux_log[i].mux.base) || in ns2_pinmux_set()
585 (mux->offset != mux_log[i].mux.offset)) in ns2_pinmux_set()
596 if (mux_log[i].mux.alt != mux->alt) { in ns2_pinmux_set()
597 dev_err(pinctrl->dev, in ns2_pinmux_set()
599 dev_err(pinctrl->dev, "func:%s grp:%s\n", in ns2_pinmux_set()
600 func->name, grp->name); in ns2_pinmux_set()
601 return -EINVAL; in ns2_pinmux_set()
607 return -EINVAL; in ns2_pinmux_set()
609 mask = mux->mask; in ns2_pinmux_set()
610 mux_log[i].mux.alt = mux->alt; in ns2_pinmux_set()
613 switch (mux->base) { in ns2_pinmux_set()
615 base_address = pinctrl->base0; in ns2_pinmux_set()
619 base_address = pinctrl->base1; in ns2_pinmux_set()
623 return -EINVAL; in ns2_pinmux_set()
626 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pinmux_set()
627 val = readl(base_address + grp->mux.offset); in ns2_pinmux_set()
628 val &= ~(mask << grp->mux.shift); in ns2_pinmux_set()
629 val |= grp->mux.alt << grp->mux.shift; in ns2_pinmux_set()
630 writel(val, (base_address + grp->mux.offset)); in ns2_pinmux_set()
631 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pinmux_set()
639 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); in ns2_pinmux_enable() local
643 if (grp_select >= pinctrl->num_groups || in ns2_pinmux_enable()
644 func_select >= pinctrl->num_functions) in ns2_pinmux_enable()
645 return -EINVAL; in ns2_pinmux_enable()
647 func = &pinctrl->functions[func_select]; in ns2_pinmux_enable()
648 grp = &pinctrl->groups[grp_select]; in ns2_pinmux_enable()
650 dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n", in ns2_pinmux_enable()
651 func_select, func->name, grp_select, grp->name); in ns2_pinmux_enable()
653 dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n", in ns2_pinmux_enable()
654 grp->mux.offset, grp->mux.shift, grp->mux.alt); in ns2_pinmux_enable()
656 return ns2_pinmux_set(pinctrl, func, grp, pinctrl->mux_log); in ns2_pinmux_enable()
662 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_set_enable() local
663 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_set_enable()
668 base_address = pinctrl->pinconf_base; in ns2_pin_set_enable()
669 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_set_enable()
670 val = readl(base_address + pin_data->pin_conf.offset); in ns2_pin_set_enable()
671 val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.input_en); in ns2_pin_set_enable()
674 val |= NS2_PIN_INPUT_EN_MASK << pin_data->pin_conf.input_en; in ns2_pin_set_enable()
676 writel(val, (base_address + pin_data->pin_conf.offset)); in ns2_pin_set_enable()
677 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_set_enable()
679 dev_dbg(pctrldev->dev, "pin:%u set enable:%d\n", pin, enable); in ns2_pin_set_enable()
685 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_get_enable() local
686 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_get_enable()
690 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_get_enable()
691 enable = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset); in ns2_pin_get_enable()
692 enable = (enable >> pin_data->pin_conf.input_en) & in ns2_pin_get_enable()
694 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_get_enable()
701 dev_dbg(pctrldev->dev, "pin:%u get disable:%d\n", pin, enable); in ns2_pin_get_enable()
708 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_set_slew() local
709 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_set_slew()
714 base_address = pinctrl->pinconf_base; in ns2_pin_set_slew()
715 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_set_slew()
716 val = readl(base_address + pin_data->pin_conf.offset); in ns2_pin_set_slew()
717 val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift); in ns2_pin_set_slew()
720 val |= NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift; in ns2_pin_set_slew()
722 writel(val, (base_address + pin_data->pin_conf.offset)); in ns2_pin_set_slew()
723 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_set_slew()
725 dev_dbg(pctrldev->dev, "pin:%u set slew:%d\n", pin, slew); in ns2_pin_set_slew()
732 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_get_slew() local
733 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_get_slew()
737 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_get_slew()
738 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset); in ns2_pin_get_slew()
739 *slew = (val >> pin_data->pin_conf.src_shift) & NS2_PIN_SRC_MASK; in ns2_pin_get_slew()
740 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_get_slew()
742 dev_dbg(pctrldev->dev, "pin:%u get slew:%d\n", pin, *slew); in ns2_pin_get_slew()
749 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_set_pull() local
750 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_set_pull()
755 base_address = pinctrl->pinconf_base; in ns2_pin_set_pull()
756 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_set_pull()
757 val = readl(base_address + pin_data->pin_conf.offset); in ns2_pin_set_pull()
758 val &= ~(NS2_PIN_PULL_MASK << pin_data->pin_conf.pull_shift); in ns2_pin_set_pull()
761 val |= NS2_PIN_PULL_UP << pin_data->pin_conf.pull_shift; in ns2_pin_set_pull()
763 val |= NS2_PIN_PULL_DOWN << pin_data->pin_conf.pull_shift; in ns2_pin_set_pull()
764 writel(val, (base_address + pin_data->pin_conf.offset)); in ns2_pin_set_pull()
765 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_set_pull()
767 dev_dbg(pctrldev->dev, "pin:%u set pullup:%d pulldown: %d\n", in ns2_pin_set_pull()
776 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_get_pull() local
777 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_get_pull()
781 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_get_pull()
782 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset); in ns2_pin_get_pull()
783 val = (val >> pin_data->pin_conf.pull_shift) & NS2_PIN_PULL_MASK; in ns2_pin_get_pull()
792 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_get_pull()
798 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_set_strength() local
799 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_set_strength()
806 return -ENOTSUPP; in ns2_pin_set_strength()
808 base_address = pinctrl->pinconf_base; in ns2_pin_set_strength()
809 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_set_strength()
810 val = readl(base_address + pin_data->pin_conf.offset); in ns2_pin_set_strength()
811 val &= ~(NS2_PIN_DRIVE_STRENGTH_MASK << pin_data->pin_conf.drive_shift); in ns2_pin_set_strength()
812 val |= ((strength / 2) - 1) << pin_data->pin_conf.drive_shift; in ns2_pin_set_strength()
813 writel(val, (base_address + pin_data->pin_conf.offset)); in ns2_pin_set_strength()
814 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_set_strength()
816 dev_dbg(pctrldev->dev, "pin:%u set drive strength:%d mA\n", in ns2_pin_set_strength()
824 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev); in ns2_pin_get_strength() local
825 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_get_strength()
829 spin_lock_irqsave(&pinctrl->lock, flags); in ns2_pin_get_strength()
830 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset); in ns2_pin_get_strength()
831 *strength = (val >> pin_data->pin_conf.drive_shift) & in ns2_pin_get_strength()
833 *strength = (*strength + 1) * 2; in ns2_pin_get_strength()
834 spin_unlock_irqrestore(&pinctrl->lock, flags); in ns2_pin_get_strength()
836 dev_dbg(pctrldev->dev, "pin:%u get drive strength:%d mA\n", in ns2_pin_get_strength()
844 struct ns2_pin *pin_data = pctldev->desc->pins[pin].drv_data; in ns2_pin_config_get()
850 if (pin_data->pin_conf.base == -1) in ns2_pin_config_get()
851 return -ENOTSUPP; in ns2_pin_config_get()
859 return -EINVAL; in ns2_pin_config_get()
866 return -EINVAL; in ns2_pin_config_get()
873 return -EINVAL; in ns2_pin_config_get()
894 return -EINVAL; in ns2_pin_config_get()
897 return -ENOTSUPP; in ns2_pin_config_get()
904 struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data; in ns2_pin_config_set()
908 int ret = -ENOTSUPP; in ns2_pin_config_set()
910 if (pin_data->pin_conf.base == -1) in ns2_pin_config_set()
911 return -ENOTSUPP; in ns2_pin_config_set()
955 dev_err(pctrldev->dev, "invalid configuration\n"); in ns2_pin_config_set()
956 return -ENOTSUPP; in ns2_pin_config_set()
976 .name = "ns2-pinmux",
982 static int ns2_mux_log_init(struct ns2_pinctrl *pinctrl) in ns2_mux_log_init() argument
987 pinctrl->mux_log = devm_kcalloc(pinctrl->dev, NS2_NUM_IOMUX, in ns2_mux_log_init()
990 if (!pinctrl->mux_log) in ns2_mux_log_init()
991 return -ENOMEM; in ns2_mux_log_init()
994 pinctrl->mux_log[i].is_configured = false; in ns2_mux_log_init()
996 log = &pinctrl->mux_log[0]; in ns2_mux_log_init()
997 log->mux.base = NS2_PIN_MUX_BASE0; in ns2_mux_log_init()
998 log->mux.offset = 0; in ns2_mux_log_init()
999 log->mux.shift = 31; in ns2_mux_log_init()
1000 log->mux.alt = 0; in ns2_mux_log_init()
1003 * Groups 1 through 14 use two bits each in the in ns2_mux_log_init()
1007 for (i = 1; i < (NS2_NUM_IOMUX - NS2_NUM_PWM_MUX); i++) { in ns2_mux_log_init()
1008 log = &pinctrl->mux_log[i]; in ns2_mux_log_init()
1009 log->mux.base = NS2_PIN_MUX_BASE0; in ns2_mux_log_init()
1010 log->mux.offset = NS2_MUX_PAD_FUNC1_OFFSET; in ns2_mux_log_init()
1011 log->mux.shift = 32 - (i * 2); in ns2_mux_log_init()
1012 log->mux.alt = 0; in ns2_mux_log_init()
1020 log = &pinctrl->mux_log[(NS2_NUM_IOMUX - NS2_NUM_PWM_MUX) + i]; in ns2_mux_log_init()
1021 log->mux.base = NS2_PIN_MUX_BASE1; in ns2_mux_log_init()
1022 log->mux.offset = 0; in ns2_mux_log_init()
1023 log->mux.shift = i; in ns2_mux_log_init()
1024 log->mux.alt = 0; in ns2_mux_log_init()
1031 struct ns2_pinctrl *pinctrl; in ns2_pinmux_probe() local
1037 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL); in ns2_pinmux_probe()
1038 if (!pinctrl) in ns2_pinmux_probe()
1039 return -ENOMEM; in ns2_pinmux_probe()
1041 pinctrl->dev = &pdev->dev; in ns2_pinmux_probe()
1042 platform_set_drvdata(pdev, pinctrl); in ns2_pinmux_probe()
1043 spin_lock_init(&pinctrl->lock); in ns2_pinmux_probe()
1045 pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0); in ns2_pinmux_probe()
1046 if (IS_ERR(pinctrl->base0)) in ns2_pinmux_probe()
1047 return PTR_ERR(pinctrl->base0); in ns2_pinmux_probe()
1049 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); in ns2_pinmux_probe()
1051 return -EINVAL; in ns2_pinmux_probe()
1052 pinctrl->base1 = devm_ioremap(&pdev->dev, res->start, in ns2_pinmux_probe()
1054 if (!pinctrl->base1) { in ns2_pinmux_probe()
1055 dev_err(&pdev->dev, "unable to map I/O space\n"); in ns2_pinmux_probe()
1056 return -ENOMEM; in ns2_pinmux_probe()
1059 pinctrl->pinconf_base = devm_platform_ioremap_resource(pdev, 2); in ns2_pinmux_probe()
1060 if (IS_ERR(pinctrl->pinconf_base)) in ns2_pinmux_probe()
1061 return PTR_ERR(pinctrl->pinconf_base); in ns2_pinmux_probe()
1063 ret = ns2_mux_log_init(pinctrl); in ns2_pinmux_probe()
1065 dev_err(&pdev->dev, "unable to initialize IOMUX log\n"); in ns2_pinmux_probe()
1069 pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL); in ns2_pinmux_probe()
1071 return -ENOMEM; in ns2_pinmux_probe()
1079 pinctrl->groups = ns2_pin_groups; in ns2_pinmux_probe()
1080 pinctrl->num_groups = ARRAY_SIZE(ns2_pin_groups); in ns2_pinmux_probe()
1081 pinctrl->functions = ns2_pin_functions; in ns2_pinmux_probe()
1082 pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions); in ns2_pinmux_probe()
1086 pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev, in ns2_pinmux_probe()
1087 pinctrl); in ns2_pinmux_probe()
1088 if (IS_ERR(pinctrl->pctl)) { in ns2_pinmux_probe()
1089 dev_err(&pdev->dev, "unable to register IOMUX pinctrl\n"); in ns2_pinmux_probe()
1090 return PTR_ERR(pinctrl->pctl); in ns2_pinmux_probe()
1097 {.compatible = "brcm,ns2-pinmux"},
1103 .name = "ns2-pinmux",