Lines Matching +full:bit +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2017 Broadcom
9 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include "../pinctrl-utils.h"
65 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
123 * Mapping from PINCONF pins to GPIO pins is 1-to-1
131 * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
143 unsigned int shift = IPROC_GPIO_SHIFT(gpio); in iproc_set_bit() local
146 val = readl(chip->base + offset); in iproc_set_bit()
148 val |= BIT(shift); in iproc_set_bit()
150 val &= ~BIT(shift); in iproc_set_bit()
151 writel(val, chip->base + offset); in iproc_set_bit()
158 unsigned int shift = IPROC_GPIO_SHIFT(gpio); in iproc_get_bit() local
160 return !!(readl(chip->base + offset) & BIT(shift)); in iproc_get_bit()
168 int i, bit; in iproc_gpio_irq_handler() local
173 for (i = 0; i < chip->num_banks; i++) { in iproc_gpio_irq_handler()
174 unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) + in iproc_gpio_irq_handler()
177 for_each_set_bit(bit, &val, NGPIOS_PER_BANK) { in iproc_gpio_irq_handler()
178 unsigned pin = NGPIOS_PER_BANK * i + bit; in iproc_gpio_irq_handler()
179 int child_irq = irq_find_mapping(gc->irq.domain, pin); in iproc_gpio_irq_handler()
185 writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) + in iproc_gpio_irq_handler()
200 unsigned gpio = d->hwirq; in iproc_gpio_irq_ack()
203 unsigned int shift = IPROC_GPIO_SHIFT(gpio); in iproc_gpio_irq_ack() local
204 u32 val = BIT(shift); in iproc_gpio_irq_ack()
206 writel(val, chip->base + offset); in iproc_gpio_irq_ack()
210 * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt
219 unsigned gpio = d->hwirq; in iproc_gpio_irq_set_mask()
230 raw_spin_lock_irqsave(&chip->lock, flags); in iproc_gpio_irq_mask()
232 raw_spin_unlock_irqrestore(&chip->lock, flags); in iproc_gpio_irq_mask()
241 raw_spin_lock_irqsave(&chip->lock, flags); in iproc_gpio_irq_unmask()
243 raw_spin_unlock_irqrestore(&chip->lock, flags); in iproc_gpio_irq_unmask()
250 unsigned gpio = d->hwirq; in iproc_gpio_irq_set_type()
278 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n", in iproc_gpio_irq_set_type()
280 return -EINVAL; in iproc_gpio_irq_set_type()
283 raw_spin_lock_irqsave(&chip->lock, flags); in iproc_gpio_irq_set_type()
295 raw_spin_unlock_irqrestore(&chip->lock, flags); in iproc_gpio_irq_set_type()
297 dev_dbg(chip->dev, in iproc_gpio_irq_set_type()
310 unsigned gpio = gc->base + offset; in iproc_gpio_request()
313 if (!chip->pinmux_is_supported) in iproc_gpio_request()
322 unsigned gpio = gc->base + offset; in iproc_gpio_free()
324 if (!chip->pinmux_is_supported) in iproc_gpio_free()
335 raw_spin_lock_irqsave(&chip->lock, flags); in iproc_gpio_direction_input()
337 raw_spin_unlock_irqrestore(&chip->lock, flags); in iproc_gpio_direction_input()
339 dev_dbg(chip->dev, "gpio:%u set input\n", gpio); in iproc_gpio_direction_input()
350 raw_spin_lock_irqsave(&chip->lock, flags); in iproc_gpio_direction_output()
353 raw_spin_unlock_irqrestore(&chip->lock, flags); in iproc_gpio_direction_output()
355 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); in iproc_gpio_direction_output()
364 unsigned int shift = IPROC_GPIO_SHIFT(gpio); in iproc_gpio_get_direction() local
366 if (readl(chip->base + offset) & BIT(shift)) in iproc_gpio_get_direction()
377 raw_spin_lock_irqsave(&chip->lock, flags); in iproc_gpio_set()
379 raw_spin_unlock_irqrestore(&chip->lock, flags); in iproc_gpio_set()
381 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); in iproc_gpio_set()
389 unsigned int shift = IPROC_GPIO_SHIFT(gpio); in iproc_gpio_get() local
391 return !!(readl(chip->base + offset) & BIT(shift)); in iproc_gpio_get()
410 if (!chip->nr_pinconf_disable) in iproc_pinconf_param_is_disabled()
413 for (i = 0; i < chip->nr_pinconf_disable; i++) in iproc_pinconf_param_is_disabled()
414 if (chip->pinconf_disable[i] == param) in iproc_pinconf_param_is_disabled()
424 unsigned int bit, nbits = 0; in iproc_pinconf_disable_map_create() local
427 for_each_set_bit(bit, &disable_mask, map_size) in iproc_pinconf_disable_map_create()
437 chip->pinconf_disable = devm_kcalloc(chip->dev, nbits, in iproc_pinconf_disable_map_create()
438 sizeof(*chip->pinconf_disable), in iproc_pinconf_disable_map_create()
440 if (!chip->pinconf_disable) in iproc_pinconf_disable_map_create()
441 return -ENOMEM; in iproc_pinconf_disable_map_create()
443 chip->nr_pinconf_disable = nbits; in iproc_pinconf_disable_map_create()
447 for_each_set_bit(bit, &disable_mask, map_size) in iproc_pinconf_disable_map_create()
448 chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit]; in iproc_pinconf_disable_map_create()
480 unsigned int shift; in iproc_gpio_set_pull() local
483 raw_spin_lock_irqsave(&chip->lock, flags); in iproc_gpio_set_pull()
484 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) { in iproc_gpio_set_pull()
485 base = chip->io_ctrl; in iproc_gpio_set_pull()
486 shift = IPROC_GPIO_SHIFT(gpio); in iproc_gpio_set_pull()
491 /* no pull-up or pull-down */ in iproc_gpio_set_pull()
492 val_1 &= ~BIT(shift); in iproc_gpio_set_pull()
493 val_2 &= ~BIT(shift); in iproc_gpio_set_pull()
495 val_1 |= BIT(shift); in iproc_gpio_set_pull()
496 val_2 &= ~BIT(shift); in iproc_gpio_set_pull()
498 val_1 &= ~BIT(shift); in iproc_gpio_set_pull()
499 val_2 |= BIT(shift); in iproc_gpio_set_pull()
515 raw_spin_unlock_irqrestore(&chip->lock, flags); in iproc_gpio_set_pull()
516 dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up); in iproc_gpio_set_pull()
526 unsigned int shift; in iproc_gpio_get_pull() local
529 raw_spin_lock_irqsave(&chip->lock, flags); in iproc_gpio_get_pull()
530 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) { in iproc_gpio_get_pull()
531 base = chip->io_ctrl; in iproc_gpio_get_pull()
532 shift = IPROC_GPIO_SHIFT(gpio); in iproc_gpio_get_pull()
534 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift); in iproc_gpio_get_pull()
535 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift); in iproc_gpio_get_pull()
544 raw_spin_unlock_irqrestore(&chip->lock, flags); in iproc_gpio_get_pull()
547 #define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \ argument
548 ((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
550 ((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
551 ((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
557 unsigned int i, offset, shift; in iproc_gpio_set_strength() local
563 return -ENOTSUPP; in iproc_gpio_set_strength()
565 if (chip->io_ctrl) { in iproc_gpio_set_strength()
566 base = chip->io_ctrl; in iproc_gpio_set_strength()
568 base = chip->base; in iproc_gpio_set_strength()
571 shift = IPROC_GPIO_SHIFT(gpio); in iproc_gpio_set_strength()
573 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, in iproc_gpio_set_strength()
576 raw_spin_lock_irqsave(&chip->lock, flags); in iproc_gpio_set_strength()
577 strength = (strength / 2) - 1; in iproc_gpio_set_strength()
579 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type); in iproc_gpio_set_strength()
581 val &= ~BIT(shift); in iproc_gpio_set_strength()
582 val |= ((strength >> i) & 0x1) << shift; in iproc_gpio_set_strength()
585 raw_spin_unlock_irqrestore(&chip->lock, flags); in iproc_gpio_set_strength()
594 unsigned int i, offset, shift; in iproc_gpio_get_strength() local
598 if (chip->io_ctrl) { in iproc_gpio_get_strength()
599 base = chip->io_ctrl; in iproc_gpio_get_strength()
601 base = chip->base; in iproc_gpio_get_strength()
604 shift = IPROC_GPIO_SHIFT(gpio); in iproc_gpio_get_strength()
606 raw_spin_lock_irqsave(&chip->lock, flags); in iproc_gpio_get_strength()
609 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type); in iproc_gpio_get_strength()
610 val = readl(base + offset) & BIT(shift); in iproc_gpio_get_strength()
611 val >>= shift; in iproc_gpio_get_strength()
617 raw_spin_unlock_irqrestore(&chip->lock, flags); in iproc_gpio_get_strength()
633 return -ENOTSUPP; in iproc_pin_config_get()
641 return -EINVAL; in iproc_pin_config_get()
648 return -EINVAL; in iproc_pin_config_get()
655 return -EINVAL; in iproc_pin_config_get()
666 return -ENOTSUPP; in iproc_pin_config_get()
669 return -ENOTSUPP; in iproc_pin_config_get()
679 int ret = -ENOTSUPP; in iproc_pin_config_set()
685 return -ENOTSUPP; in iproc_pin_config_set()
715 dev_err(chip->dev, "invalid configuration\n"); in iproc_pin_config_set()
716 return -ENOTSUPP; in iproc_pin_config_set()
734 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
739 struct pinctrl_desc *pctldesc = &chip->pctldesc; in iproc_gpio_register_pinconf()
741 struct gpio_chip *gc = &chip->gc; in iproc_gpio_register_pinconf()
744 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL); in iproc_gpio_register_pinconf()
746 return -ENOMEM; in iproc_gpio_register_pinconf()
748 for (i = 0; i < gc->ngpio; i++) { in iproc_gpio_register_pinconf()
750 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL, in iproc_gpio_register_pinconf()
751 "gpio-%d", i); in iproc_gpio_register_pinconf()
753 return -ENOMEM; in iproc_gpio_register_pinconf()
756 pctldesc->name = dev_name(chip->dev); in iproc_gpio_register_pinconf()
757 pctldesc->pctlops = &iproc_pctrl_ops; in iproc_gpio_register_pinconf()
758 pctldesc->pins = pins; in iproc_gpio_register_pinconf()
759 pctldesc->npins = gc->ngpio; in iproc_gpio_register_pinconf()
760 pctldesc->confops = &iproc_pconf_ops; in iproc_gpio_register_pinconf()
762 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip); in iproc_gpio_register_pinconf()
763 if (IS_ERR(chip->pctl)) { in iproc_gpio_register_pinconf()
764 dev_err(chip->dev, "unable to register pinctrl device\n"); in iproc_gpio_register_pinconf()
765 return PTR_ERR(chip->pctl); in iproc_gpio_register_pinconf()
772 { .compatible = "brcm,iproc-gpio" },
773 { .compatible = "brcm,cygnus-ccm-gpio" },
774 { .compatible = "brcm,cygnus-asiu-gpio" },
775 { .compatible = "brcm,cygnus-crmu-gpio" },
776 { .compatible = "brcm,iproc-nsp-gpio" },
777 { .compatible = "brcm,iproc-stingray-gpio" },
783 struct device *dev = &pdev->dev; in iproc_gpio_probe()
793 if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio")) in iproc_gpio_probe()
794 pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH); in iproc_gpio_probe()
796 else if (of_device_is_compatible(dev->of_node, in iproc_gpio_probe()
797 "brcm,iproc-stingray-gpio")) in iproc_gpio_probe()
802 return -ENOMEM; in iproc_gpio_probe()
804 chip->dev = dev; in iproc_gpio_probe()
807 chip->base = devm_platform_ioremap_resource(pdev, 0); in iproc_gpio_probe()
808 if (IS_ERR(chip->base)) { in iproc_gpio_probe()
810 return PTR_ERR(chip->base); in iproc_gpio_probe()
815 chip->io_ctrl = devm_ioremap_resource(dev, res); in iproc_gpio_probe()
816 if (IS_ERR(chip->io_ctrl)) { in iproc_gpio_probe()
818 return PTR_ERR(chip->io_ctrl); in iproc_gpio_probe()
820 if (of_device_is_compatible(dev->of_node, in iproc_gpio_probe()
821 "brcm,cygnus-ccm-gpio")) in iproc_gpio_probe()
827 chip->io_ctrl_type = io_ctrl_type; in iproc_gpio_probe()
829 if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) { in iproc_gpio_probe()
830 dev_err(&pdev->dev, "missing ngpios DT property\n"); in iproc_gpio_probe()
831 return -ENODEV; in iproc_gpio_probe()
834 raw_spin_lock_init(&chip->lock); in iproc_gpio_probe()
836 gc = &chip->gc; in iproc_gpio_probe()
837 gc->base = -1; in iproc_gpio_probe()
838 gc->ngpio = ngpios; in iproc_gpio_probe()
839 chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK; in iproc_gpio_probe()
840 gc->label = dev_name(dev); in iproc_gpio_probe()
841 gc->parent = dev; in iproc_gpio_probe()
842 gc->of_node = dev->of_node; in iproc_gpio_probe()
843 gc->request = iproc_gpio_request; in iproc_gpio_probe()
844 gc->free = iproc_gpio_free; in iproc_gpio_probe()
845 gc->direction_input = iproc_gpio_direction_input; in iproc_gpio_probe()
846 gc->direction_output = iproc_gpio_direction_output; in iproc_gpio_probe()
847 gc->get_direction = iproc_gpio_get_direction; in iproc_gpio_probe()
848 gc->set = iproc_gpio_set; in iproc_gpio_probe()
849 gc->get = iproc_gpio_get; in iproc_gpio_probe()
851 chip->pinmux_is_supported = of_property_read_bool(dev->of_node, in iproc_gpio_probe()
852 "gpio-ranges"); in iproc_gpio_probe()
860 irqc = &chip->irqchip; in iproc_gpio_probe()
861 irqc->name = dev_name(dev); in iproc_gpio_probe()
862 irqc->irq_ack = iproc_gpio_irq_ack; in iproc_gpio_probe()
863 irqc->irq_mask = iproc_gpio_irq_mask; in iproc_gpio_probe()
864 irqc->irq_unmask = iproc_gpio_irq_unmask; in iproc_gpio_probe()
865 irqc->irq_set_type = iproc_gpio_irq_set_type; in iproc_gpio_probe()
866 irqc->irq_enable = iproc_gpio_irq_unmask; in iproc_gpio_probe()
867 irqc->irq_disable = iproc_gpio_irq_mask; in iproc_gpio_probe()
869 girq = &gc->irq; in iproc_gpio_probe()
870 girq->chip = irqc; in iproc_gpio_probe()
871 girq->parent_handler = iproc_gpio_irq_handler; in iproc_gpio_probe()
872 girq->num_parents = 1; in iproc_gpio_probe()
873 girq->parents = devm_kcalloc(dev, 1, in iproc_gpio_probe()
874 sizeof(*girq->parents), in iproc_gpio_probe()
876 if (!girq->parents) in iproc_gpio_probe()
877 return -ENOMEM; in iproc_gpio_probe()
878 girq->parents[0] = irq; in iproc_gpio_probe()
879 girq->default_type = IRQ_TYPE_NONE; in iproc_gpio_probe()
880 girq->handler = handle_bad_irq; in iproc_gpio_probe()
917 .name = "iproc-gpio",