202 struct wiz {  struct
229 static int wiz_reset(struct wiz *wiz)  in wiz_reset()  argument
233 	ret = regmap_field_write(wiz->por_en, 0x1);  in wiz_reset()
239 	ret = regmap_field_write(wiz->por_en, 0x0);  in wiz_reset()
246 static int wiz_mode_select(struct wiz *wiz)  in wiz_mode_select()  argument
248 	u32 num_lanes = wiz->num_lanes;  in wiz_mode_select()
254 		if (wiz->lane_phy_type[i] == PHY_TYPE_DP)  in wiz_mode_select()
259 		ret = regmap_field_write(wiz->p_standard_mode[i], mode);  in wiz_mode_select()
267 static int wiz_init_raw_interface(struct wiz *wiz, bool enable)  in wiz_init_raw_interface()  argument
269 	u32 num_lanes = wiz->num_lanes;  in wiz_init_raw_interface()
274 		ret = regmap_field_write(wiz->p_align[i], enable);  in wiz_init_raw_interface()
278 		ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);  in wiz_init_raw_interface()
286 static int wiz_init(struct wiz *wiz)  in wiz_init()  argument
288 	struct device *dev = wiz->dev;  in wiz_init()
291 	ret = wiz_reset(wiz);  in wiz_init()
293 		dev_err(dev, "WIZ reset failed\n");  in wiz_init()
297 	ret = wiz_mode_select(wiz);  in wiz_init()
299 		dev_err(dev, "WIZ mode select failed\n");  in wiz_init()
303 	ret = wiz_init_raw_interface(wiz, true);  in wiz_init()
305 		dev_err(dev, "WIZ interface initialization failed\n");  in wiz_init()
312 static int wiz_regfield_init(struct wiz *wiz)  in wiz_regfield_init()  argument
316 	struct regmap *regmap = wiz->regmap;  in wiz_regfield_init()
317 	int num_lanes = wiz->num_lanes;  in wiz_regfield_init()
318 	struct device *dev = wiz->dev;  in wiz_regfield_init()
321 	wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);  in wiz_regfield_init()
322 	if (IS_ERR(wiz->por_en)) {  in wiz_regfield_init()
324 		return PTR_ERR(wiz->por_en);  in wiz_regfield_init()
327 	wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
329 	if (IS_ERR(wiz->phy_reset_n)) {  in wiz_regfield_init()
331 		return PTR_ERR(wiz->phy_reset_n);  in wiz_regfield_init()
334 	wiz->pma_cmn_refclk_int_mode =  in wiz_regfield_init()
336 	if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {  in wiz_regfield_init()
338 		return PTR_ERR(wiz->pma_cmn_refclk_int_mode);  in wiz_regfield_init()
341 	wiz->pma_cmn_refclk_mode =  in wiz_regfield_init()
343 	if (IS_ERR(wiz->pma_cmn_refclk_mode)) {  in wiz_regfield_init()
345 		return PTR_ERR(wiz->pma_cmn_refclk_mode);  in wiz_regfield_init()
348 	clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV];  in wiz_regfield_init()
356 	if (wiz->type == J721E_WIZ_16G) {  in wiz_regfield_init()
357 		clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV];  in wiz_regfield_init()
367 	clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK];  in wiz_regfield_init()
375 	clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK];  in wiz_regfield_init()
383 	clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG];  in wiz_regfield_init()
384 	if (wiz->type == J721E_WIZ_10G)  in wiz_regfield_init()
399 		wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
401 		if (IS_ERR(wiz->p_enable[i])) {  in wiz_regfield_init()
403 			return PTR_ERR(wiz->p_enable[i]);  in wiz_regfield_init()
406 		wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
408 		if (IS_ERR(wiz->p_align[i])) {  in wiz_regfield_init()
410 			return PTR_ERR(wiz->p_align[i]);  in wiz_regfield_init()
413 		wiz->p_raw_auto_start[i] =  in wiz_regfield_init()
415 		if (IS_ERR(wiz->p_raw_auto_start[i])) {  in wiz_regfield_init()
418 			return PTR_ERR(wiz->p_raw_auto_start[i]);  in wiz_regfield_init()
421 		wiz->p_standard_mode[i] =  in wiz_regfield_init()
423 		if (IS_ERR(wiz->p_standard_mode[i])) {  in wiz_regfield_init()
426 			return PTR_ERR(wiz->p_standard_mode[i]);  in wiz_regfield_init()
430 	wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,  in wiz_regfield_init()
432 	if (IS_ERR(wiz->typec_ln10_swap)) {  in wiz_regfield_init()
434 		return PTR_ERR(wiz->typec_ln10_swap);  in wiz_regfield_init()
465 static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node,  in wiz_mux_clk_register()  argument
468 	struct device *dev = wiz->dev;  in wiz_mux_clk_register()
560 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,  in wiz_div_clk_register()  argument
564 	struct device *dev = wiz->dev;  in wiz_div_clk_register()
608 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)  in wiz_clock_cleanup()  argument
610 	struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;  in wiz_clock_cleanup()
620 	for (i = 0; i < wiz->clk_div_sel_num; i++) {  in wiz_clock_cleanup()
627 static int wiz_clock_init(struct wiz *wiz, struct device_node *node)  in wiz_clock_init()  argument
629 	struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;  in wiz_clock_init()
630 	struct device *dev = wiz->dev;  in wiz_clock_init()
647 		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);  in wiz_clock_init()
649 		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);  in wiz_clock_init()
660 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);  in wiz_clock_init()
662 		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);  in wiz_clock_init()
673 		ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field,  in wiz_clock_init()
685 	for (i = 0; i < wiz->clk_div_sel_num; i++) {  in wiz_clock_init()
694 		ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field,  in wiz_clock_init()
708 	wiz_clock_cleanup(wiz, node);  in wiz_clock_init()
717 	struct wiz *wiz = dev_get_drvdata(dev);  in wiz_phy_reset_assert()  local
721 		ret = regmap_field_write(wiz->phy_reset_n, false);  in wiz_phy_reset_assert()
725 	ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);  in wiz_phy_reset_assert()
733 	struct wiz *wiz = dev_get_drvdata(dev);  in wiz_phy_reset_deassert()  local
737 	if (id == 0 && wiz->gpio_typec_dir) {  in wiz_phy_reset_deassert()
738 		if (wiz->typec_dir_delay)  in wiz_phy_reset_deassert()
739 			msleep_interruptible(wiz->typec_dir_delay);  in wiz_phy_reset_deassert()
741 		if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))  in wiz_phy_reset_deassert()
742 			regmap_field_write(wiz->typec_ln10_swap, 1);  in wiz_phy_reset_deassert()
744 			regmap_field_write(wiz->typec_ln10_swap, 0);  in wiz_phy_reset_deassert()
748 		ret = regmap_field_write(wiz->phy_reset_n, true);  in wiz_phy_reset_deassert()
752 	if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)  in wiz_phy_reset_deassert()
753 		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);  in wiz_phy_reset_deassert()
755 		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);  in wiz_phy_reset_deassert()
774 		.compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G
777 		.compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
783 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)  in wiz_get_lane_phy_types()  argument
811 			wiz->lane_phy_type[i] = phy_type;  in wiz_get_lane_phy_types()
827 	struct wiz *wiz;  in wiz_probe()  local
831 	wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);  in wiz_probe()
832 	if (!wiz)  in wiz_probe()
835 	wiz->type = (enum wiz_type)of_device_get_match_data(dev);  in wiz_probe()
874 	wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",  in wiz_probe()
876 	if (IS_ERR(wiz->gpio_typec_dir)) {  in wiz_probe()
877 		ret = PTR_ERR(wiz->gpio_typec_dir);  in wiz_probe()
884 	if (wiz->gpio_typec_dir) {  in wiz_probe()
886 					   &wiz->typec_dir_delay);  in wiz_probe()
894 			wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;  in wiz_probe()
896 		if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||  in wiz_probe()
897 		    wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {  in wiz_probe()
904 	ret = wiz_get_lane_phy_types(dev, wiz);  in wiz_probe()
908 	wiz->dev = dev;  in wiz_probe()
909 	wiz->regmap = regmap;  in wiz_probe()
910 	wiz->num_lanes = num_lanes;  in wiz_probe()
911 	if (wiz->type == J721E_WIZ_10G)  in wiz_probe()
912 		wiz->clk_mux_sel = clk_mux_sel_10g;  in wiz_probe()
914 		wiz->clk_mux_sel = clk_mux_sel_16g;  in wiz_probe()
916 	wiz->clk_div_sel = clk_div_sel;  in wiz_probe()
918 	if (wiz->type == J721E_WIZ_10G)  in wiz_probe()
919 		wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;  in wiz_probe()
921 		wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;  in wiz_probe()
923 	platform_set_drvdata(pdev, wiz);  in wiz_probe()
925 	ret = wiz_regfield_init(wiz);  in wiz_probe()
931 	phy_reset_dev = &wiz->wiz_phy_reset_dev;  in wiz_probe()
952 	ret = wiz_clock_init(wiz, node);  in wiz_probe()
958 	ret = wiz_init(wiz);  in wiz_probe()
960 		dev_err(dev, "WIZ initialization failed\n");  in wiz_probe()
970 	wiz->serdes_pdev = serdes_pdev;  in wiz_probe()
976 	wiz_clock_cleanup(wiz, node);  in wiz_probe()
993 	struct wiz *wiz;  in wiz_remove()  local
995 	wiz = dev_get_drvdata(dev);  in wiz_remove()
996 	serdes_pdev = wiz->serdes_pdev;  in wiz_remove()
999 	wiz_clock_cleanup(wiz, node);  in wiz_remove()
1010 		.name	= "wiz",
1017 MODULE_DESCRIPTION("TI J721E WIZ driver");