Lines Matching +full:refclk +full:- +full:dig
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
11 #include <linux/clk-provider.h>
22 #include <linux/reset-controller.h>
144 .node_name = "pll0-refclk",
148 .node_name = "pll1-refclk",
152 .node_name = "refclk-dig",
163 .node_name = "pll0-refclk",
167 .node_name = "pll1-refclk",
171 .node_name = "refclk-dig",
186 .node_name = "cmn-refclk-dig-div",
190 .node_name = "cmn-refclk1-dig-div",
233 ret = regmap_field_write(wiz->por_en, 0x1); in wiz_reset()
239 ret = regmap_field_write(wiz->por_en, 0x0); in wiz_reset()
248 u32 num_lanes = wiz->num_lanes; in wiz_mode_select()
254 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) in wiz_mode_select()
259 ret = regmap_field_write(wiz->p_standard_mode[i], mode); in wiz_mode_select()
269 u32 num_lanes = wiz->num_lanes; in wiz_init_raw_interface()
274 ret = regmap_field_write(wiz->p_align[i], enable); in wiz_init_raw_interface()
278 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); in wiz_init_raw_interface()
288 struct device *dev = wiz->dev; in wiz_init()
316 struct regmap *regmap = wiz->regmap; in wiz_regfield_init()
317 int num_lanes = wiz->num_lanes; in wiz_regfield_init()
318 struct device *dev = wiz->dev; in wiz_regfield_init()
321 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); in wiz_regfield_init()
322 if (IS_ERR(wiz->por_en)) { in wiz_regfield_init()
324 return PTR_ERR(wiz->por_en); in wiz_regfield_init()
327 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
329 if (IS_ERR(wiz->phy_reset_n)) { in wiz_regfield_init()
331 return PTR_ERR(wiz->phy_reset_n); in wiz_regfield_init()
334 wiz->pma_cmn_refclk_int_mode = in wiz_regfield_init()
336 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { in wiz_regfield_init()
338 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); in wiz_regfield_init()
341 wiz->pma_cmn_refclk_mode = in wiz_regfield_init()
343 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { in wiz_regfield_init()
345 return PTR_ERR(wiz->pma_cmn_refclk_mode); in wiz_regfield_init()
348 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV]; in wiz_regfield_init()
349 clk_div_sel->field = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
351 if (IS_ERR(clk_div_sel->field)) { in wiz_regfield_init()
353 return PTR_ERR(clk_div_sel->field); in wiz_regfield_init()
356 if (wiz->type == J721E_WIZ_16G) { in wiz_regfield_init()
357 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV]; in wiz_regfield_init()
358 clk_div_sel->field = in wiz_regfield_init()
361 if (IS_ERR(clk_div_sel->field)) { in wiz_regfield_init()
363 return PTR_ERR(clk_div_sel->field); in wiz_regfield_init()
367 clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK]; in wiz_regfield_init()
368 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
370 if (IS_ERR(clk_mux_sel->field)) { in wiz_regfield_init()
372 return PTR_ERR(clk_mux_sel->field); in wiz_regfield_init()
375 clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK]; in wiz_regfield_init()
376 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
378 if (IS_ERR(clk_mux_sel->field)) { in wiz_regfield_init()
380 return PTR_ERR(clk_mux_sel->field); in wiz_regfield_init()
383 clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG]; in wiz_regfield_init()
384 if (wiz->type == J721E_WIZ_10G) in wiz_regfield_init()
385 clk_mux_sel->field = in wiz_regfield_init()
389 clk_mux_sel->field = in wiz_regfield_init()
393 if (IS_ERR(clk_mux_sel->field)) { in wiz_regfield_init()
395 return PTR_ERR(clk_mux_sel->field); in wiz_regfield_init()
399 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
401 if (IS_ERR(wiz->p_enable[i])) { in wiz_regfield_init()
403 return PTR_ERR(wiz->p_enable[i]); in wiz_regfield_init()
406 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
408 if (IS_ERR(wiz->p_align[i])) { in wiz_regfield_init()
410 return PTR_ERR(wiz->p_align[i]); in wiz_regfield_init()
413 wiz->p_raw_auto_start[i] = in wiz_regfield_init()
415 if (IS_ERR(wiz->p_raw_auto_start[i])) { in wiz_regfield_init()
418 return PTR_ERR(wiz->p_raw_auto_start[i]); in wiz_regfield_init()
421 wiz->p_standard_mode[i] = in wiz_regfield_init()
423 if (IS_ERR(wiz->p_standard_mode[i])) { in wiz_regfield_init()
426 return PTR_ERR(wiz->p_standard_mode[i]); in wiz_regfield_init()
430 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, in wiz_regfield_init()
432 if (IS_ERR(wiz->typec_ln10_swap)) { in wiz_regfield_init()
434 return PTR_ERR(wiz->typec_ln10_swap); in wiz_regfield_init()
443 struct regmap_field *field = mux->field; in wiz_clk_mux_get_parent()
447 return clk_mux_val_to_index(hw, mux->table, 0, val); in wiz_clk_mux_get_parent()
453 struct regmap_field *field = mux->field; in wiz_clk_mux_set_parent()
456 val = mux->table[index]; in wiz_clk_mux_set_parent()
468 struct device *dev = wiz->dev; in wiz_mux_clk_register()
479 return -ENOMEM; in wiz_mux_clk_register()
484 return -EINVAL; in wiz_mux_clk_register()
490 return -ENOMEM; in wiz_mux_clk_register()
495 node->name); in wiz_mux_clk_register()
497 init = &mux->clk_data; in wiz_mux_clk_register()
499 init->ops = &wiz_clk_mux_ops; in wiz_mux_clk_register()
500 init->flags = CLK_SET_RATE_NO_REPARENT; in wiz_mux_clk_register()
501 init->parent_names = parent_names; in wiz_mux_clk_register()
502 init->num_parents = num_parents; in wiz_mux_clk_register()
503 init->name = clk_name; in wiz_mux_clk_register()
505 mux->field = field; in wiz_mux_clk_register()
506 mux->table = table; in wiz_mux_clk_register()
507 mux->hw.init = init; in wiz_mux_clk_register()
509 clk = devm_clk_register(dev, &mux->hw); in wiz_mux_clk_register()
524 struct regmap_field *field = div->field; in wiz_clk_div_recalc_rate()
529 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); in wiz_clk_div_recalc_rate()
537 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); in wiz_clk_div_round_rate()
544 struct regmap_field *field = div->field; in wiz_clk_div_set_rate()
547 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); in wiz_clk_div_set_rate()
564 struct device *dev = wiz->dev; in wiz_div_clk_register()
574 return -ENOMEM; in wiz_div_clk_register()
577 node->name); in wiz_div_clk_register()
581 return -ENOMEM; in wiz_div_clk_register()
585 init = &div->clk_data; in wiz_div_clk_register()
587 init->ops = &wiz_clk_div_ops; in wiz_div_clk_register()
588 init->flags = 0; in wiz_div_clk_register()
589 init->parent_names = parent_names; in wiz_div_clk_register()
590 init->num_parents = 1; in wiz_div_clk_register()
591 init->name = clk_name; in wiz_div_clk_register()
593 div->field = field; in wiz_div_clk_register()
594 div->table = table; in wiz_div_clk_register()
595 div->hw.init = init; in wiz_div_clk_register()
597 clk = devm_clk_register(dev, &div->hw); in wiz_div_clk_register()
610 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; in wiz_clock_cleanup()
620 for (i = 0; i < wiz->clk_div_sel_num; i++) { in wiz_clock_cleanup()
629 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; in wiz_clock_init()
630 struct device *dev = wiz->dev; in wiz_clock_init()
647 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); in wiz_clock_init()
649 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); in wiz_clock_init()
660 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); in wiz_clock_init()
662 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); in wiz_clock_init()
669 ret = -EINVAL; in wiz_clock_init()
685 for (i = 0; i < wiz->clk_div_sel_num; i++) { in wiz_clock_init()
690 ret = -EINVAL; in wiz_clock_init()
716 struct device *dev = rcdev->dev; in wiz_phy_reset_assert()
721 ret = regmap_field_write(wiz->phy_reset_n, false); in wiz_phy_reset_assert()
725 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); in wiz_phy_reset_assert()
732 struct device *dev = rcdev->dev; in wiz_phy_reset_deassert()
736 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ in wiz_phy_reset_deassert()
737 if (id == 0 && wiz->gpio_typec_dir) { in wiz_phy_reset_deassert()
738 if (wiz->typec_dir_delay) in wiz_phy_reset_deassert()
739 msleep_interruptible(wiz->typec_dir_delay); in wiz_phy_reset_deassert()
741 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) in wiz_phy_reset_deassert()
742 regmap_field_write(wiz->typec_ln10_swap, 1); in wiz_phy_reset_deassert()
744 regmap_field_write(wiz->typec_ln10_swap, 0); in wiz_phy_reset_deassert()
748 ret = regmap_field_write(wiz->phy_reset_n, true); in wiz_phy_reset_deassert()
752 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) in wiz_phy_reset_deassert()
753 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); in wiz_phy_reset_deassert()
755 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); in wiz_phy_reset_deassert()
774 .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G
777 .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
787 serdes = of_get_child_by_name(dev->of_node, "serdes"); in wiz_get_lane_phy_types()
789 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__); in wiz_get_lane_phy_types()
790 return -EINVAL; in wiz_get_lane_phy_types()
801 __func__, subnode->name, ret); in wiz_get_lane_phy_types()
804 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); in wiz_get_lane_phy_types()
805 of_property_read_u32(subnode, "cdns,phy-type", &phy_type); in wiz_get_lane_phy_types()
807 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, in wiz_get_lane_phy_types()
808 reg, reg + num_lanes - 1, phy_type); in wiz_get_lane_phy_types()
811 wiz->lane_phy_type[i] = phy_type; in wiz_get_lane_phy_types()
820 struct device *dev = &pdev->dev; in wiz_probe()
821 struct device_node *node = dev->of_node; in wiz_probe()
833 return -ENOMEM; in wiz_probe()
835 wiz->type = (enum wiz_type)of_device_get_match_data(dev); in wiz_probe()
840 return -ENODEV; in wiz_probe()
851 ret = -ENOMEM; in wiz_probe()
862 ret = of_property_read_u32(node, "num-lanes", &num_lanes); in wiz_probe()
864 dev_err(dev, "Failed to read num-lanes property\n"); in wiz_probe()
870 ret = -ENODEV; in wiz_probe()
874 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", in wiz_probe()
876 if (IS_ERR(wiz->gpio_typec_dir)) { in wiz_probe()
877 ret = PTR_ERR(wiz->gpio_typec_dir); in wiz_probe()
878 if (ret != -EPROBE_DEFER) in wiz_probe()
879 dev_err(dev, "Failed to request typec-dir gpio: %d\n", in wiz_probe()
884 if (wiz->gpio_typec_dir) { in wiz_probe()
885 ret = of_property_read_u32(node, "typec-dir-debounce-ms", in wiz_probe()
886 &wiz->typec_dir_delay); in wiz_probe()
887 if (ret && ret != -EINVAL) { in wiz_probe()
888 dev_err(dev, "Invalid typec-dir-debounce property\n"); in wiz_probe()
892 /* use min. debounce from Type-C spec if not provided in DT */ in wiz_probe()
893 if (ret == -EINVAL) in wiz_probe()
894 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; in wiz_probe()
896 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || in wiz_probe()
897 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { in wiz_probe()
898 ret = -EINVAL; in wiz_probe()
899 dev_err(dev, "Invalid typec-dir-debounce property\n"); in wiz_probe()
908 wiz->dev = dev; in wiz_probe()
909 wiz->regmap = regmap; in wiz_probe()
910 wiz->num_lanes = num_lanes; in wiz_probe()
911 if (wiz->type == J721E_WIZ_10G) in wiz_probe()
912 wiz->clk_mux_sel = clk_mux_sel_10g; in wiz_probe()
914 wiz->clk_mux_sel = clk_mux_sel_16g; in wiz_probe()
916 wiz->clk_div_sel = clk_div_sel; in wiz_probe()
918 if (wiz->type == J721E_WIZ_10G) in wiz_probe()
919 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G; in wiz_probe()
921 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G; in wiz_probe()
931 phy_reset_dev = &wiz->wiz_phy_reset_dev; in wiz_probe()
932 phy_reset_dev->dev = dev; in wiz_probe()
933 phy_reset_dev->ops = &wiz_phy_reset_ops, in wiz_probe()
934 phy_reset_dev->owner = THIS_MODULE, in wiz_probe()
935 phy_reset_dev->of_node = node; in wiz_probe()
937 phy_reset_dev->nr_resets = num_lanes + 1; in wiz_probe()
967 ret = -ENOMEM; in wiz_probe()
970 wiz->serdes_pdev = serdes_pdev; in wiz_probe()
990 struct device *dev = &pdev->dev; in wiz_remove()
991 struct device_node *node = dev->of_node; in wiz_remove()
996 serdes_pdev = wiz->serdes_pdev; in wiz_remove()
998 of_platform_device_destroy(&serdes_pdev->dev, NULL); in wiz_remove()