Lines Matching +full:pre +full:- +full:emphasis
1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
92 { {0x3, 0x1, 0x0}, {0x5, 0x1, 0x7}, {0x6, 0x1, 0x6}, { -1, -1, -1} },
93 { {0x5, 0x1, 0x0}, {0x7, 0x1, 0x4}, { -1, -1, -1}, { -1, -1, -1} },
94 { {0x7, 0x1, 0x0}, { -1, -1, -1}, { -1, -1, -1}, { -1, -1, -1} },
103 amp = vp[dp->voltage[lane]][dp->pre[lane]].amp; in rockchip_edp_phy_set_voltage()
104 amp_scale = vp[dp->voltage[lane]][dp->pre[lane]].amp_scale; in rockchip_edp_phy_set_voltage()
105 emp = vp[dp->voltage[lane]][dp->pre[lane]].emp; in rockchip_edp_phy_set_voltage()
109 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, in rockchip_edp_phy_set_voltage()
112 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4, in rockchip_edp_phy_set_voltage()
115 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, in rockchip_edp_phy_set_voltage()
120 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, in rockchip_edp_phy_set_voltage()
123 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4, in rockchip_edp_phy_set_voltage()
126 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, in rockchip_edp_phy_set_voltage()
131 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, in rockchip_edp_phy_set_voltage()
134 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4, in rockchip_edp_phy_set_voltage()
137 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, in rockchip_edp_phy_set_voltage()
142 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON3, in rockchip_edp_phy_set_voltage()
145 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON4, in rockchip_edp_phy_set_voltage()
148 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, in rockchip_edp_phy_set_voltage()
160 for (lane = 0; lane < dp->lanes; lane++) in rockchip_edp_phy_set_voltages()
172 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, in rockchip_edp_phy_set_rate()
177 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE, in rockchip_edp_phy_set_rate()
179 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL, in rockchip_edp_phy_set_rate()
182 switch (dp->link_rate) { in rockchip_edp_phy_set_rate()
184 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON1, in rockchip_edp_phy_set_rate()
187 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON2, in rockchip_edp_phy_set_rate()
192 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON8, in rockchip_edp_phy_set_rate()
195 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON9, in rockchip_edp_phy_set_rate()
200 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON1, in rockchip_edp_phy_set_rate()
203 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON2, in rockchip_edp_phy_set_rate()
208 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON8, in rockchip_edp_phy_set_rate()
211 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON9, in rockchip_edp_phy_set_rate()
217 if (dp->ssc) in rockchip_edp_phy_set_rate()
218 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON6, in rockchip_edp_phy_set_rate()
224 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON6, in rockchip_edp_phy_set_rate()
228 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL, in rockchip_edp_phy_set_rate()
230 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_TX_PD, in rockchip_edp_phy_set_rate()
231 FIELD_PREP(EDP_PHY_TX_PD, ~GENMASK(dp->lanes - 1, 0))); in rockchip_edp_phy_set_rate()
232 ret = regmap_read_poll_timeout(edpphy->grf, EDP_PHY_GRF_STATUS0, in rockchip_edp_phy_set_rate()
235 dev_err(edpphy->dev, "pll is not ready: %d\n", ret); in rockchip_edp_phy_set_rate()
239 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE, in rockchip_edp_phy_set_rate()
241 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_TX_IDLE, in rockchip_edp_phy_set_rate()
242 FIELD_PREP(EDP_PHY_TX_IDLE, ~GENMASK(dp->lanes - 1, 0))); in rockchip_edp_phy_set_rate()
253 if (dp->set_rate) { in rockchip_edp_phy_verify_config()
254 switch (dp->link_rate) { in rockchip_edp_phy_verify_config()
260 return -EINVAL; in rockchip_edp_phy_verify_config()
265 switch (dp->lanes) { in rockchip_edp_phy_verify_config()
272 return -EINVAL; in rockchip_edp_phy_verify_config()
276 * If changing voltages is required, check swing and pre-emphasis in rockchip_edp_phy_verify_config()
277 * levels, per-lane. in rockchip_edp_phy_verify_config()
279 if (dp->set_voltages) { in rockchip_edp_phy_verify_config()
281 for (i = 0; i < dp->lanes; i++) { in rockchip_edp_phy_verify_config()
282 if (dp->voltage[i] > 3 || dp->pre[i] > 3) in rockchip_edp_phy_verify_config()
283 return -EINVAL; in rockchip_edp_phy_verify_config()
286 * Sum of voltage swing and pre-emphasis levels cannot in rockchip_edp_phy_verify_config()
289 if (dp->voltage[i] + dp->pre[i] > 3) in rockchip_edp_phy_verify_config()
290 return -EINVAL; in rockchip_edp_phy_verify_config()
303 ret = rockchip_edp_phy_verify_config(edpphy, &opts->dp); in rockchip_edp_phy_configure()
305 dev_err(edpphy->dev, "invalid params for phy configure\n"); in rockchip_edp_phy_configure()
309 if (opts->dp.set_rate) { in rockchip_edp_phy_configure()
310 ret = rockchip_edp_phy_set_rate(edpphy, &opts->dp); in rockchip_edp_phy_configure()
312 dev_err(edpphy->dev, in rockchip_edp_phy_configure()
318 if (opts->dp.set_voltages) { in rockchip_edp_phy_configure()
319 ret = rockchip_edp_phy_set_voltages(edpphy, &opts->dp); in rockchip_edp_phy_configure()
321 dev_err(edpphy->dev, in rockchip_edp_phy_configure()
334 regmap_read(edpphy->grf, EDP_PHY_GRF_STATUS0, &val); in rockchip_edp_phy_enabled()
343 clk_prepare_enable(edpphy->refclk); in rockchip_edp_phy_power_on()
348 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10, in rockchip_edp_phy_power_on()
353 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, in rockchip_edp_phy_power_on()
360 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON11, in rockchip_edp_phy_power_on()
370 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10, in rockchip_edp_phy_power_on()
376 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10, in rockchip_edp_phy_power_on()
388 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, in rockchip_edp_phy_power_off()
393 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON5, EDP_PHY_TX_MODE, in rockchip_edp_phy_power_off()
395 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON0, EDP_PHY_PD_PLL, in rockchip_edp_phy_power_off()
397 rockchip_grf_write(edpphy->grf, EDP_PHY_GRF_CON10, in rockchip_edp_phy_power_off()
403 clk_disable_unprepare(edpphy->refclk); in rockchip_edp_phy_power_off()
417 struct device *dev = &pdev->dev; in rockchip_edp_phy_probe()
425 return -ENOMEM; in rockchip_edp_phy_probe()
427 edpphy->dev = dev; in rockchip_edp_phy_probe()
429 edpphy->grf = syscon_node_to_regmap(dev->parent->of_node); in rockchip_edp_phy_probe()
430 if (IS_ERR(edpphy->grf)) { in rockchip_edp_phy_probe()
431 ret = PTR_ERR(edpphy->grf); in rockchip_edp_phy_probe()
436 edpphy->refclk = devm_clk_get(dev, "refclk"); in rockchip_edp_phy_probe()
437 if (IS_ERR(edpphy->refclk)) { in rockchip_edp_phy_probe()
438 ret = PTR_ERR(edpphy->refclk); in rockchip_edp_phy_probe()
462 { .compatible = "rockchip,rk3568-edp-phy", },
469 .name = "rockchip-edpphy-naneng",
476 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");