605 static inline void write_grf_reg(struct mipidphy_priv *priv,  in write_grf_reg()  function
644 	write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);  in mipidphy0_wr_reg()
645 	write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_code);  in mipidphy0_wr_reg()
646 	write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 1);  in mipidphy0_wr_reg()
647 	write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 0);  in mipidphy0_wr_reg()
648 	write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 0);  in mipidphy0_wr_reg()
649 	write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_data);  in mipidphy0_wr_reg()
650 	write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);  in mipidphy0_wr_reg()
844 		write_grf_reg(priv, GRF_DPHY_SEL, newval);  in rk1126_mipidphy_dphy_sel()
1119 	write_grf_reg(priv, GRF_ISP_MIPI_CSI_HOST_SEL, 1);  in rk3368_mipidphy_individual_init()
1128 	write_grf_reg(priv, GRF_DPHY_TX1RX1_SRC_SEL, 0);  in rk3399_mipidphy_individual_init()
1129 	write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0);  in rk3399_mipidphy_individual_init()
1130 	write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 0);  in rk3399_mipidphy_individual_init()
1132 	write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);  in rk3399_mipidphy_individual_init()
1154 		write_grf_reg(priv, GRF_DPHY_SEL, val | sel);  in rv1126_mipidphy_individual_init()
1189 	write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 0);  in mipidphy_rx_stream_on()
1197 	write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);  in mipidphy_rx_stream_on()
1198 	write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 1);  in mipidphy_rx_stream_on()
1214 	write_grf_reg(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf);  in mipidphy_rx_stream_on()
1215 	write_grf_reg(priv, GRF_DPHY_RX0_FORCERXMODE, 0);  in mipidphy_rx_stream_on()
1216 	write_grf_reg(priv, GRF_DPHY_RX0_TURNREQUEST, 0);  in mipidphy_rx_stream_on()
1220 	write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 0);  in mipidphy_rx_stream_on()
1239 	write_grf_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(sensor->lanes - 1, 0));  in mipidphy_rx_stream_on()
1291 	write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 1);  in mipidphy_txrx_stream_on()
1292 	write_grf_reg(priv, GRF_DSI_CSI_TESTBUS_SEL, 1);  in mipidphy_txrx_stream_on()
1293 	write_grf_reg(priv, GRF_DPHY_RX1_SRC_SEL, 1);  in mipidphy_txrx_stream_on()
1299 	write_grf_reg(priv, GRF_DPHY_TX1RX1_SRC_SEL, 0);  in mipidphy_txrx_stream_on()
1318 	write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0);  in mipidphy_txrx_stream_on()
1324 	write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 1);  in mipidphy_txrx_stream_on()
1327 	write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCERXMODE, 0);  in mipidphy_txrx_stream_on()
1328 	write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCETXSTOPMODE, 0);  in mipidphy_txrx_stream_on()
1329 	write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNREQUEST, 0);  in mipidphy_txrx_stream_on()
1330 	write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNDISABLE, 0xf);  in mipidphy_txrx_stream_on()
1360 	write_grf_reg(priv, GRF_DPHY_TX1RX1_ENABLE,  in mipidphy_txrx_stream_on()
1398 	write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);  in csi_mipidphy_stream_on()
1451 	write_grf_reg(priv, GRF_DPHY_CSIPHY_FORCERXMODE, 0x0);  in csi_mipidphy_stream_on()
1491 	write_grf_reg(priv, GRF_DPHY_CLK_INV_SEL, 0x1);  in csi_mipidphy_stream_on()
1492 	write_grf_reg(priv, GRF_DPHY_CSIPHY_CLKLANE_EN, 0x1);  in csi_mipidphy_stream_on()
1493 	write_grf_reg(priv, GRF_DPHY_CSIPHY_DATALANE_EN,  in csi_mipidphy_stream_on()