668 static inline void write_csiphy_reg(struct mipidphy_priv *priv,  in write_csiphy_reg()  function
714 	write_csiphy_reg(priv, offset, val);  in csi_mipidphy_wr_ths_settle()
1401 	write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe4);  in csi_mipidphy_stream_on()
1404 	write_csiphy_reg(priv, CSIPHY_CTRL_LANE_ENABLE,  in csi_mipidphy_stream_on()
1409 	write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe0);  in csi_mipidphy_stream_on()
1414 		write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1e);  in csi_mipidphy_stream_on()
1415 		write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1f);  in csi_mipidphy_stream_on()
1421 			write_csiphy_reg(priv, CSIPHY_CLK_MODE, clk_mode);  in csi_mipidphy_stream_on()
1425 		write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x3e);  in csi_mipidphy_stream_on()
1427 		write_csiphy_reg(priv, CSIPHY_MIPI_LVDS_MODEL, 0x4);  in csi_mipidphy_stream_on()
1447 		write_csiphy_reg(priv, CSIPHY_LVDS_MODE, val);  in csi_mipidphy_stream_on()
1455 		write_csiphy_reg(priv, CSIPHY_CLK_CALIB_ENABLE, 0x80);  in csi_mipidphy_stream_on()
1457 			write_csiphy_reg(priv, CSIPHY_LANE0_CALIB_ENABLE, 0x80);  in csi_mipidphy_stream_on()
1459 			write_csiphy_reg(priv, CSIPHY_LANE1_CALIB_ENABLE, 0x80);  in csi_mipidphy_stream_on()
1461 			write_csiphy_reg(priv, CSIPHY_LANE2_CALIB_ENABLE, 0x80);  in csi_mipidphy_stream_on()
1463 			write_csiphy_reg(priv, CSIPHY_LANE3_CALIB_ENABLE, 0x80);  in csi_mipidphy_stream_on()
1502 	write_csiphy_reg(priv, CSIPHY_CTRL_LANE_ENABLE, 0x01);  in csi_mipidphy_stream_off()
1504 	write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe3);  in csi_mipidphy_stream_off()