Lines Matching +full:pre +full:- +full:emphasis
104 * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration.
105 * @u2_pre_emp: usb2-phy pre-emphasis tuning.
106 * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning.
107 * @u2_odt_tuning: usb2-phy odt 45ohm tuning.
157 unsigned int tmp = desired ? reg->dvalue : reg->rvalue; in param_write()
160 mask = GENMASK(reg->bitend, reg->bitstart); in param_write()
161 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in param_write()
162 ret = regmap_write(base, reg->offset, val); in param_write()
173 unsigned int mask = GENMASK(reg->bitend, reg->bitstart); in param_exped()
175 ret = regmap_read(base, reg->offset, &orig); in param_exped()
179 tmp = (orig & mask) >> reg->bitstart; in param_exped()
187 if (!u3phy->vbus) in rockchip_set_vbus_power()
190 if (en && !u3phy->vbus_enabled) { in rockchip_set_vbus_power()
191 ret = regulator_enable(u3phy->vbus); in rockchip_set_vbus_power()
193 dev_err(u3phy->dev, in rockchip_set_vbus_power()
195 } else if (!en && u3phy->vbus_enabled) { in rockchip_set_vbus_power()
196 ret = regulator_disable(u3phy->vbus); in rockchip_set_vbus_power()
200 u3phy->vbus_enabled = en; in rockchip_set_vbus_power()
207 struct rockchip_u3phy *u3phy = s->private; in rockchip_u3phy_usb2_only_show()
209 if (param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) in rockchip_u3phy_usb2_only_show()
210 dev_info(u3phy->dev, "u2\n"); in rockchip_u3phy_usb2_only_show()
212 dev_info(u3phy->dev, "u3\n"); in rockchip_u3phy_usb2_only_show()
221 inode->i_private); in rockchip_u3phy_usb2_only_open()
228 struct seq_file *s = file->private_data; in rockchip_u3phy_usb2_only_write()
229 struct rockchip_u3phy *u3phy = s->private; in rockchip_u3phy_usb2_only_write()
234 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) in rockchip_u3phy_usb2_only_write()
235 return -EFAULT; in rockchip_u3phy_usb2_only_write()
238 param_exped(u3phy->u3phy_grf, in rockchip_u3phy_usb2_only_write()
239 &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) { in rockchip_u3phy_usb2_only_write()
240 dev_info(u3phy->dev, "Set usb3.0 and usb2.0 mode successfully\n"); in rockchip_u3phy_usb2_only_write()
244 param_write(u3phy->grf, in rockchip_u3phy_usb2_only_write()
245 &u3phy->cfgs->grfcfg.u3_disable, false); in rockchip_u3phy_usb2_only_write()
246 param_write(u3phy->u3phy_grf, in rockchip_u3phy_usb2_only_write()
247 &u3phy->cfgs->grfcfg.u2_only_ctrl, false); in rockchip_u3phy_usb2_only_write()
250 u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_usb2_only_write()
252 if (u3phy_port->type == U3PHY_TYPE_PIPE) in rockchip_u3phy_usb2_only_write()
253 writel(0x30, u3phy_port->base + 0xd8); in rockchip_u3phy_usb2_only_write()
256 atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL); in rockchip_u3phy_usb2_only_write()
260 param_exped(u3phy->u3phy_grf, in rockchip_u3phy_usb2_only_write()
261 &u3phy->cfgs->grfcfg.u2_only_ctrl, 0)) { in rockchip_u3phy_usb2_only_write()
262 dev_info(u3phy->dev, "Set usb2.0 only mode successfully\n"); in rockchip_u3phy_usb2_only_write()
266 param_write(u3phy->grf, in rockchip_u3phy_usb2_only_write()
267 &u3phy->cfgs->grfcfg.u3_disable, true); in rockchip_u3phy_usb2_only_write()
268 param_write(u3phy->u3phy_grf, in rockchip_u3phy_usb2_only_write()
269 &u3phy->cfgs->grfcfg.u2_only_ctrl, true); in rockchip_u3phy_usb2_only_write()
272 u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_usb2_only_write()
274 if (u3phy_port->type == U3PHY_TYPE_PIPE) in rockchip_u3phy_usb2_only_write()
275 writel(0x20, u3phy_port->base + 0xd8); in rockchip_u3phy_usb2_only_write()
278 atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL); in rockchip_u3phy_usb2_only_write()
282 dev_info(u3phy->dev, "Same or illegal mode\n"); in rockchip_u3phy_usb2_only_write()
300 root = debugfs_create_dir(dev_name(u3phy->dev), NULL); in rockchip_u3phy_debugfs_init()
309 return "u3phy-u2-por"; in get_rest_name()
311 return "u3phy-u3-por"; in get_rest_name()
313 return "u3phy-pipe-mac"; in get_rest_name()
315 return "u3phy-utmi-mac"; in get_rest_name()
317 return "u3phy-utmi-apb"; in get_rest_name()
319 return "u3phy-pipe-apb"; in get_rest_name()
331 dev_dbg(u3phy->dev, "deassert APB bus interface reset\n"); in rockchip_u3phy_rest_deassert()
333 if (u3phy->rsts[rst]) in rockchip_u3phy_rest_deassert()
334 reset_control_deassert(u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
340 dev_dbg(u3phy->dev, "deassert u2 and u3 phy power on reset\n"); in rockchip_u3phy_rest_deassert()
342 if (u3phy->rsts[rst]) in rockchip_u3phy_rest_deassert()
343 reset_control_deassert(u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
349 dev_dbg(u3phy->dev, "deassert pipe and utmi MAC reset\n"); in rockchip_u3phy_rest_deassert()
351 if (u3phy->rsts[rst]) in rockchip_u3phy_rest_deassert()
352 reset_control_deassert(u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
360 dev_dbg(u3phy->dev, "assert u3phy reset\n"); in rockchip_u3phy_rest_assert()
362 if (u3phy->rsts[rst]) in rockchip_u3phy_rest_assert()
363 reset_control_assert(u3phy->rsts[rst]); in rockchip_u3phy_rest_assert()
370 for (clk = 0; clk < U3PHY_MAX_CLKS && u3phy->clks[clk]; clk++) { in rockchip_u3phy_clk_enable()
371 ret = clk_prepare_enable(u3phy->clks[clk]); in rockchip_u3phy_clk_enable()
378 while (--clk >= 0) in rockchip_u3phy_clk_enable()
379 clk_disable_unprepare(u3phy->clks[clk]); in rockchip_u3phy_clk_enable()
387 for (clk = U3PHY_MAX_CLKS - 1; clk >= 0; clk--) in rockchip_u3phy_clk_disable()
388 if (u3phy->clks[clk]) in rockchip_u3phy_clk_disable()
389 clk_disable_unprepare(u3phy->clks[clk]); in rockchip_u3phy_clk_disable()
405 struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); in rockchip_u3phy_power_on()
408 dev_info(&u3phy_port->phy->dev, "u3phy %s power on\n", in rockchip_u3phy_power_on()
409 (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3"); in rockchip_u3phy_power_on()
411 if (!u3phy_port->suspended) in rockchip_u3phy_power_on()
418 if (u3phy_port->type == U3PHY_TYPE_UTMI) { in rockchip_u3phy_power_on()
419 param_write(u3phy->u3phy_grf, in rockchip_u3phy_power_on()
420 &u3phy->cfgs->grfcfg.um_suspend, false); in rockchip_u3phy_power_on()
423 if (param_exped(u3phy->u3phy_grf, in rockchip_u3phy_power_on()
424 &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P2)) in rockchip_u3phy_power_on()
427 if (u3phy->cfgs->phy_pipe_power) { in rockchip_u3phy_power_on()
428 dev_dbg(u3phy->dev, "do pipe power up\n"); in rockchip_u3phy_power_on()
429 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, true); in rockchip_u3phy_power_on()
433 param_write(u3phy->u3phy_grf, in rockchip_u3phy_power_on()
434 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true); in rockchip_u3phy_power_on()
438 param_write(u3phy->u3phy_grf, in rockchip_u3phy_power_on()
439 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P2], in rockchip_u3phy_power_on()
446 u3phy_port->suspended = false; in rockchip_u3phy_power_on()
453 struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent); in rockchip_u3phy_power_off()
455 dev_info(&u3phy_port->phy->dev, "u3phy %s power off\n", in rockchip_u3phy_power_off()
456 (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3"); in rockchip_u3phy_power_off()
458 if (u3phy_port->suspended) in rockchip_u3phy_power_off()
461 if (u3phy_port->type == U3PHY_TYPE_UTMI) { in rockchip_u3phy_power_off()
462 param_write(u3phy->u3phy_grf, in rockchip_u3phy_power_off()
463 &u3phy->cfgs->grfcfg.um_suspend, true); in rockchip_u3phy_power_off()
466 if (param_exped(u3phy->u3phy_grf, in rockchip_u3phy_power_off()
467 &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P3)) in rockchip_u3phy_power_off()
471 param_write(u3phy->u3phy_grf, in rockchip_u3phy_power_off()
472 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true); in rockchip_u3phy_power_off()
476 param_write(u3phy->u3phy_grf, in rockchip_u3phy_power_off()
477 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P3], true); in rockchip_u3phy_power_off()
480 if (u3phy->cfgs->phy_pipe_power) { in rockchip_u3phy_power_off()
481 dev_dbg(u3phy->dev, "do pipe power down\n"); in rockchip_u3phy_power_off()
482 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, false); in rockchip_u3phy_power_off()
488 u3phy_port->suspended = true; in rockchip_u3phy_power_off()
498 struct device_node *phy_np = args->np; in rockchip_u3phy_xlate()
501 if (args->args_count != 1) { in rockchip_u3phy_xlate()
503 return ERR_PTR(-EINVAL); in rockchip_u3phy_xlate()
507 if (phy_np == u3phy->ports[index].phy->dev.of_node) { in rockchip_u3phy_xlate()
508 u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_xlate()
515 return ERR_PTR(-EINVAL); in rockchip_u3phy_xlate()
518 return u3phy_port->phy; in rockchip_u3phy_xlate()
530 * The function manage host-phy port state and suspend/resume phy port
544 dev_get_drvdata(u3phy_port->phy->dev.parent); in rockchip_u3phy_um_sm_work()
545 unsigned int sh = u3phy->cfgs->grfcfg.um_hstdct.bitend - in rockchip_u3phy_um_sm_work()
546 u3phy->cfgs->grfcfg.um_hstdct.bitstart + 1; in rockchip_u3phy_um_sm_work()
551 mutex_lock(&u3phy_port->mutex); in rockchip_u3phy_um_sm_work()
553 ret = regmap_read(u3phy->u3phy_grf, in rockchip_u3phy_um_sm_work()
554 u3phy->cfgs->grfcfg.um_ls.offset, &ul); in rockchip_u3phy_um_sm_work()
558 ret = regmap_read(u3phy->u3phy_grf, in rockchip_u3phy_um_sm_work()
559 u3phy->cfgs->grfcfg.um_hstdct.offset, &uhd); in rockchip_u3phy_um_sm_work()
563 uhd_mask = GENMASK(u3phy->cfgs->grfcfg.um_hstdct.bitend, in rockchip_u3phy_um_sm_work()
564 u3phy->cfgs->grfcfg.um_hstdct.bitstart); in rockchip_u3phy_um_sm_work()
565 ul_mask = GENMASK(u3phy->cfgs->grfcfg.um_ls.bitend, in rockchip_u3phy_um_sm_work()
566 u3phy->cfgs->grfcfg.um_ls.bitstart); in rockchip_u3phy_um_sm_work()
569 state = ((uhd & uhd_mask) >> u3phy->cfgs->grfcfg.um_hstdct.bitstart) | in rockchip_u3phy_um_sm_work()
570 (((ul & ul_mask) >> u3phy->cfgs->grfcfg.um_ls.bitstart) << sh); in rockchip_u3phy_um_sm_work()
574 dev_dbg(&u3phy_port->phy->dev, "HS online\n"); in rockchip_u3phy_um_sm_work()
582 * Plus, there are two cases, one is D- Line pull-up, and D+ in rockchip_u3phy_um_sm_work()
583 * line pull-down, the state is 4; another is D+ line pull-up, in rockchip_u3phy_um_sm_work()
584 * and D- line pull-down, the state is 2. in rockchip_u3phy_um_sm_work()
586 if (!u3phy_port->suspended) { in rockchip_u3phy_um_sm_work()
587 /* D- line pull-up, D+ line pull-down */ in rockchip_u3phy_um_sm_work()
588 dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n"); in rockchip_u3phy_um_sm_work()
593 if (u3phy_port->suspended) { in rockchip_u3phy_um_sm_work()
594 dev_dbg(&u3phy_port->phy->dev, "Connected\n"); in rockchip_u3phy_um_sm_work()
595 rockchip_u3phy_power_on(u3phy_port->phy); in rockchip_u3phy_um_sm_work()
596 u3phy_port->suspended = false; in rockchip_u3phy_um_sm_work()
598 /* D+ line pull-up, D- line pull-down */ in rockchip_u3phy_um_sm_work()
599 dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n"); in rockchip_u3phy_um_sm_work()
603 if (!u3phy_port->suspended) { in rockchip_u3phy_um_sm_work()
604 dev_dbg(&u3phy_port->phy->dev, "Disconnected\n"); in rockchip_u3phy_um_sm_work()
605 rockchip_u3phy_power_off(u3phy_port->phy); in rockchip_u3phy_um_sm_work()
606 u3phy_port->suspended = true; in rockchip_u3phy_um_sm_work()
611 * plug-in irq. in rockchip_u3phy_um_sm_work()
613 param_write(u3phy->u3phy_grf, in rockchip_u3phy_um_sm_work()
614 &u3phy->cfgs->grfcfg.ls_det_st, true); in rockchip_u3phy_um_sm_work()
615 param_write(u3phy->u3phy_grf, in rockchip_u3phy_um_sm_work()
616 &u3phy->cfgs->grfcfg.ls_det_en, true); in rockchip_u3phy_um_sm_work()
622 mutex_unlock(&u3phy_port->mutex); in rockchip_u3phy_um_sm_work()
625 dev_dbg(&u3phy_port->phy->dev, "unknown phy state\n"); in rockchip_u3phy_um_sm_work()
630 mutex_unlock(&u3phy_port->mutex); in rockchip_u3phy_um_sm_work()
631 schedule_delayed_work(&u3phy_port->um_sm_work, SCHEDULE_DELAY); in rockchip_u3phy_um_sm_work()
638 dev_get_drvdata(u3phy_port->phy->dev.parent); in rockchip_u3phy_um_ls_irq()
640 if (!param_exped(u3phy->u3phy_grf, in rockchip_u3phy_um_ls_irq()
641 &u3phy->cfgs->grfcfg.ls_det_st, in rockchip_u3phy_um_ls_irq()
642 u3phy->cfgs->grfcfg.ls_det_st.dvalue)) in rockchip_u3phy_um_ls_irq()
645 dev_dbg(u3phy->dev, "utmi linestate interrupt\n"); in rockchip_u3phy_um_ls_irq()
646 mutex_lock(&u3phy_port->mutex); in rockchip_u3phy_um_ls_irq()
649 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_en, false); in rockchip_u3phy_um_ls_irq()
650 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_st, true); in rockchip_u3phy_um_ls_irq()
652 mutex_unlock(&u3phy_port->mutex); in rockchip_u3phy_um_ls_irq()
659 if (u3phy_port->suspended) { in rockchip_u3phy_um_ls_irq()
660 dev_dbg(u3phy->dev, "schedule utmi sm work\n"); in rockchip_u3phy_um_ls_irq()
661 rockchip_u3phy_um_sm_work(&u3phy_port->um_sm_work.work); in rockchip_u3phy_um_ls_irq()
671 struct device *dev = &pdev->dev; in rockchip_u3phy_parse_dt()
672 struct device_node *np = dev->of_node; in rockchip_u3phy_parse_dt()
675 u3phy->um_ls_irq = platform_get_irq_byname(pdev, "linestate"); in rockchip_u3phy_parse_dt()
676 if (u3phy->um_ls_irq < 0) { in rockchip_u3phy_parse_dt()
678 return -ENXIO; in rockchip_u3phy_parse_dt()
682 u3phy->vbus = devm_regulator_get_optional(dev, "vbus"); in rockchip_u3phy_parse_dt()
683 if (IS_ERR(u3phy->vbus)) { in rockchip_u3phy_parse_dt()
684 ret = PTR_ERR(u3phy->vbus); in rockchip_u3phy_parse_dt()
685 if (ret == -EPROBE_DEFER) in rockchip_u3phy_parse_dt()
689 u3phy->vbus = NULL; in rockchip_u3phy_parse_dt()
693 u3phy->clks[clk] = of_clk_get(np, clk); in rockchip_u3phy_parse_dt()
694 if (IS_ERR(u3phy->clks[clk])) { in rockchip_u3phy_parse_dt()
695 ret = PTR_ERR(u3phy->clks[clk]); in rockchip_u3phy_parse_dt()
696 if (ret == -EPROBE_DEFER) in rockchip_u3phy_parse_dt()
698 u3phy->clks[clk] = NULL; in rockchip_u3phy_parse_dt()
704 u3phy->rsts[i] = devm_reset_control_get(dev, get_rest_name(i)); in rockchip_u3phy_parse_dt()
705 if (IS_ERR(u3phy->rsts[i])) { in rockchip_u3phy_parse_dt()
708 u3phy->rsts[i] = NULL; in rockchip_u3phy_parse_dt()
715 while (--clk >= 0) in rockchip_u3phy_parse_dt()
716 clk_put(u3phy->clks[clk]); in rockchip_u3phy_parse_dt()
728 dev_dbg(u3phy->dev, "u3phy port initialize\n"); in rockchip_u3phy_port_init()
730 mutex_init(&u3phy_port->mutex); in rockchip_u3phy_port_init()
731 u3phy_port->suspended = true; /* initial status */ in rockchip_u3phy_port_init()
733 phy = devm_phy_create(u3phy->dev, child_np, &rockchip_u3phy_ops); in rockchip_u3phy_port_init()
735 dev_err(u3phy->dev, "failed to create phy\n"); in rockchip_u3phy_port_init()
739 u3phy_port->phy = phy; in rockchip_u3phy_port_init()
743 dev_err(u3phy->dev, "failed to get address resource(np-%s)\n", in rockchip_u3phy_port_init()
744 child_np->name); in rockchip_u3phy_port_init()
748 u3phy_port->base = devm_ioremap_resource(&u3phy_port->phy->dev, &res); in rockchip_u3phy_port_init()
749 if (IS_ERR(u3phy_port->base)) { in rockchip_u3phy_port_init()
750 dev_err(u3phy->dev, "failed to remap phy regs\n"); in rockchip_u3phy_port_init()
751 return PTR_ERR(u3phy_port->base); in rockchip_u3phy_port_init()
754 if (!of_node_cmp(child_np->name, "pipe")) { in rockchip_u3phy_port_init()
755 u3phy_port->type = U3PHY_TYPE_PIPE; in rockchip_u3phy_port_init()
756 u3phy_port->refclk_25m_quirk = in rockchip_u3phy_port_init()
758 "rockchip,refclk-25m-quirk"); in rockchip_u3phy_port_init()
760 u3phy_port->type = U3PHY_TYPE_UTMI; in rockchip_u3phy_port_init()
761 INIT_DELAYED_WORK(&u3phy_port->um_sm_work, in rockchip_u3phy_port_init()
764 ret = devm_request_threaded_irq(u3phy->dev, u3phy->um_ls_irq, in rockchip_u3phy_port_init()
769 dev_err(u3phy->dev, "failed to request utmi linestate irq handle\n"); in rockchip_u3phy_port_init()
774 if (u3phy->cfgs->phy_tuning) { in rockchip_u3phy_port_init()
775 dev_dbg(u3phy->dev, "do u3phy tuning\n"); in rockchip_u3phy_port_init()
776 ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np); in rockchip_u3phy_port_init()
781 phy_set_drvdata(u3phy_port->phy, u3phy_port); in rockchip_u3phy_port_init()
801 if (u3phy->rsts[rst] && rst != UTMI_APB_RSTN && in rockchip_u3phy_on_shutdown()
803 reset_control_assert(u3phy->rsts[rst]); in rockchip_u3phy_on_shutdown()
813 dev_info(u3phy->dev, "%s device has disconnected\n", in rockchip_u3phy_on_disconnect()
817 atomic_notifier_call_chain(&usb_phy->notifier, 0, NULL); in rockchip_u3phy_on_disconnect()
824 struct device *dev = &pdev->dev; in rockchip_u3phy_probe()
825 struct device_node *np = dev->of_node; in rockchip_u3phy_probe()
834 match = of_match_device(dev->driver->of_match_table, dev); in rockchip_u3phy_probe()
835 if (!match || !match->data) { in rockchip_u3phy_probe()
836 dev_err(dev, "phy-cfgs are not assigned!\n"); in rockchip_u3phy_probe()
837 return -EINVAL; in rockchip_u3phy_probe()
842 return -ENOMEM; in rockchip_u3phy_probe()
844 u3phy->u3phy_grf = in rockchip_u3phy_probe()
846 if (IS_ERR(u3phy->u3phy_grf)) in rockchip_u3phy_probe()
847 return PTR_ERR(u3phy->u3phy_grf); in rockchip_u3phy_probe()
849 u3phy->grf = in rockchip_u3phy_probe()
851 if (IS_ERR(u3phy->grf)) { in rockchip_u3phy_probe()
853 return PTR_ERR(u3phy->grf); in rockchip_u3phy_probe()
858 np->name); in rockchip_u3phy_probe()
859 return -EINVAL; in rockchip_u3phy_probe()
862 u3phy->dev = dev; in rockchip_u3phy_probe()
863 u3phy->vbus_enabled = false; in rockchip_u3phy_probe()
864 phy_cfgs = match->data; in rockchip_u3phy_probe()
871 u3phy->cfgs = &phy_cfgs[index]; in rockchip_u3phy_probe()
878 if (!u3phy->cfgs) { in rockchip_u3phy_probe()
879 dev_err(dev, "no phy-cfgs can be matched with %s node\n", in rockchip_u3phy_probe()
880 np->name); in rockchip_u3phy_probe()
881 return -EINVAL; in rockchip_u3phy_probe()
901 struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_probe()
903 u3phy_port->index = index; in rockchip_u3phy_probe()
924 u3phy->usb_phy.dev = dev; in rockchip_u3phy_probe()
925 u3phy->usb_phy.init = rockchip_u3phy_on_init; in rockchip_u3phy_probe()
926 u3phy->usb_phy.shutdown = rockchip_u3phy_on_shutdown; in rockchip_u3phy_probe()
927 u3phy->usb_phy.notify_disconnect = rockchip_u3phy_on_disconnect; in rockchip_u3phy_probe()
928 usb_add_phy(&u3phy->usb_phy, USB_PHY_TYPE_USB3); in rockchip_u3phy_probe()
929 ATOMIC_INIT_NOTIFIER_HEAD(&u3phy->usb_phy.notifier); in rockchip_u3phy_probe()
948 reg = readl(u3phy_port->base + 0x1a8); in rk3328_u3phy_pipe_power()
950 writel(reg, u3phy_port->base + 0x1a8); in rk3328_u3phy_pipe_power()
952 reg = readl(u3phy_port->base + 0x044); in rk3328_u3phy_pipe_power()
954 writel(reg, u3phy_port->base + 0x044); in rk3328_u3phy_pipe_power()
956 reg = readl(u3phy_port->base + 0x150); in rk3328_u3phy_pipe_power()
958 writel(reg, u3phy_port->base + 0x150); in rk3328_u3phy_pipe_power()
960 reg = readl(u3phy_port->base + 0x080); in rk3328_u3phy_pipe_power()
962 writel(reg, u3phy_port->base + 0x080); in rk3328_u3phy_pipe_power()
964 reg = readl(u3phy_port->base + 0x0c0); in rk3328_u3phy_pipe_power()
967 writel(reg, u3phy_port->base + 0x0c0); in rk3328_u3phy_pipe_power()
971 reg = readl(u3phy_port->base + 0x1a8); in rk3328_u3phy_pipe_power()
973 writel(reg, u3phy_port->base + 0x1a8); in rk3328_u3phy_pipe_power()
975 reg = readl(u3phy_port->base + 0x044); in rk3328_u3phy_pipe_power()
977 writel(reg, u3phy_port->base + 0x044); in rk3328_u3phy_pipe_power()
979 reg = readl(u3phy_port->base + 0x150); in rk3328_u3phy_pipe_power()
981 writel(reg, u3phy_port->base + 0x150); in rk3328_u3phy_pipe_power()
983 reg = readl(u3phy_port->base + 0x080); in rk3328_u3phy_pipe_power()
985 writel(reg, u3phy_port->base + 0x080); in rk3328_u3phy_pipe_power()
987 reg = readl(u3phy_port->base + 0x0c0); in rk3328_u3phy_pipe_power()
990 writel(reg, u3phy_port->base + 0x0c0); in rk3328_u3phy_pipe_power()
1000 if (u3phy_port->type == U3PHY_TYPE_UTMI) { in rk3328_u3phy_tuning()
1002 * For rk3328 SoC, pre-emphasis and pre-emphasis strength must in rk3328_u3phy_tuning()
1010 /* {bits[2:0]=111}: always enable pre-emphasis */ in rk3328_u3phy_tuning()
1011 u3phy->apbcfg.u2_pre_emp = 0x0f; in rk3328_u3phy_tuning()
1013 /* {bits[5:3]=000}: pre-emphasis strength as the weakest */ in rk3328_u3phy_tuning()
1014 u3phy->apbcfg.u2_pre_emp_sth = 0x41; in rk3328_u3phy_tuning()
1017 u3phy->apbcfg.u2_odt_tuning = 0xb5; in rk3328_u3phy_tuning()
1019 of_property_read_u32(child_np, "rockchip,odt-val-tuning", in rk3328_u3phy_tuning()
1020 &u3phy->apbcfg.u2_odt_tuning); in rk3328_u3phy_tuning()
1022 writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030); in rk3328_u3phy_tuning()
1023 writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040); in rk3328_u3phy_tuning()
1024 writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c); in rk3328_u3phy_tuning()
1025 } else if (u3phy_port->type == U3PHY_TYPE_PIPE) { in rk3328_u3phy_tuning()
1026 if (u3phy_port->refclk_25m_quirk) { in rk3328_u3phy_tuning()
1027 dev_dbg(u3phy->dev, "switch to 25m refclk\n"); in rk3328_u3phy_tuning()
1029 writel(0x64, u3phy_port->base + 0x11c); in rk3328_u3phy_tuning()
1030 writel(0x64, u3phy_port->base + 0x028); in rk3328_u3phy_tuning()
1031 writel(0x01, u3phy_port->base + 0x020); in rk3328_u3phy_tuning()
1032 writel(0x21, u3phy_port->base + 0x030); in rk3328_u3phy_tuning()
1033 writel(0x06, u3phy_port->base + 0x108); in rk3328_u3phy_tuning()
1034 writel(0x00, u3phy_port->base + 0x118); in rk3328_u3phy_tuning()
1037 writel(0x80, u3phy_port->base + 0x10c); in rk3328_u3phy_tuning()
1038 writel(0x01, u3phy_port->base + 0x118); in rk3328_u3phy_tuning()
1039 writel(0x38, u3phy_port->base + 0x11c); in rk3328_u3phy_tuning()
1040 writel(0x83, u3phy_port->base + 0x020); in rk3328_u3phy_tuning()
1041 writel(0x02, u3phy_port->base + 0x108); in rk3328_u3phy_tuning()
1046 writel(0x08, u3phy_port->base + 0x000); in rk3328_u3phy_tuning()
1047 writel(0x0c, u3phy_port->base + 0x120); in rk3328_u3phy_tuning()
1050 writel(0x70, u3phy_port->base + 0x150); in rk3328_u3phy_tuning()
1051 writel(0x12, u3phy_port->base + 0x0c8); in rk3328_u3phy_tuning()
1052 writel(0x05, u3phy_port->base + 0x148); in rk3328_u3phy_tuning()
1053 writel(0x08, u3phy_port->base + 0x068); in rk3328_u3phy_tuning()
1054 writel(0xf0, u3phy_port->base + 0x1c4); in rk3328_u3phy_tuning()
1055 writel(0xff, u3phy_port->base + 0x070); in rk3328_u3phy_tuning()
1056 writel(0x0f, u3phy_port->base + 0x06c); in rk3328_u3phy_tuning()
1057 writel(0xe0, u3phy_port->base + 0x060); in rk3328_u3phy_tuning()
1064 writel(0x08, u3phy_port->base + 0x180); in rk3328_u3phy_tuning()
1066 dev_err(u3phy->dev, "invalid u3phy port type\n"); in rk3328_u3phy_tuning()
1067 return -EINVAL; in rk3328_u3phy_tuning()
1097 { .compatible = "rockchip,rk3328-u3phy", .data = &rk3328_u3phy_cfgs },
1105 .name = "rockchip-u3phy",
1111 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1112 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");