Lines Matching refs:inno
280 int (*init)(struct inno_hdmi_phy *inno);
281 int (*power_on)(struct inno_hdmi_phy *inno,
284 void (*power_off)(struct inno_hdmi_phy *inno);
382 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val) in inno_write() argument
384 regmap_write(inno->regmap, reg * 4, val); in inno_write()
387 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg) in inno_read() argument
391 regmap_read(inno->regmap, reg * 4, &val); in inno_read()
396 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, in inno_update_bits() argument
399 regmap_update_bits(inno->regmap, reg * 4, mask, val); in inno_update_bits()
402 #define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \ argument
403 regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \
406 static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, in inno_hdmi_phy_get_tmdsclk() argument
409 int bus_width = phy_get_bus_width(inno->phy); in inno_hdmi_phy_get_tmdsclk()
426 struct inno_hdmi_phy *inno = dev_id; in inno_hdmi_phy_rk3328_hardirq() local
429 intr_stat1 = inno_read(inno, 0x04); in inno_hdmi_phy_rk3328_hardirq()
430 intr_stat2 = inno_read(inno, 0x06); in inno_hdmi_phy_rk3328_hardirq()
431 intr_stat3 = inno_read(inno, 0x08); in inno_hdmi_phy_rk3328_hardirq()
434 inno_write(inno, 0x04, intr_stat1); in inno_hdmi_phy_rk3328_hardirq()
436 inno_write(inno, 0x06, intr_stat2); in inno_hdmi_phy_rk3328_hardirq()
438 inno_write(inno, 0x08, intr_stat3); in inno_hdmi_phy_rk3328_hardirq()
448 struct inno_hdmi_phy *inno = dev_id; in inno_hdmi_phy_rk3328_irq() local
450 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0); in inno_hdmi_phy_rk3328_irq()
452 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN); in inno_hdmi_phy_rk3328_irq()
459 struct inno_hdmi_phy *inno = phy_get_drvdata(phy); in inno_hdmi_phy_power_on() local
461 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table; in inno_hdmi_phy_power_on()
462 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, in inno_hdmi_phy_power_on()
463 inno->pixclock); in inno_hdmi_phy_power_on()
467 dev_err(inno->dev, "TMDS clock is zero!\n"); in inno_hdmi_phy_power_on()
471 if (!inno->plat_data->ops->power_on) in inno_hdmi_phy_power_on()
476 cfg->version & inno->chip_version) in inno_hdmi_phy_power_on()
486 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); in inno_hdmi_phy_power_on()
488 ret = clk_prepare_enable(inno->phyclk); in inno_hdmi_phy_power_on()
492 ret = inno->plat_data->ops->power_on(inno, cfg, phy_cfg); in inno_hdmi_phy_power_on()
494 clk_disable_unprepare(inno->phyclk); in inno_hdmi_phy_power_on()
503 struct inno_hdmi_phy *inno = phy_get_drvdata(phy); in inno_hdmi_phy_power_off() local
505 if (!inno->plat_data->ops->power_off) in inno_hdmi_phy_power_off()
508 inno->plat_data->ops->power_off(inno); in inno_hdmi_phy_power_off()
510 clk_disable_unprepare(inno->phyclk); in inno_hdmi_phy_power_off()
512 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); in inno_hdmi_phy_power_off()
524 struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi_phy *inno, in inno_hdmi_phy_get_pre_pll_cfg() argument
528 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); in inno_hdmi_phy_get_pre_pll_cfg()
542 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_rk3228_clk_is_prepared() local
545 status = inno_read(inno, 0xe0) & RK3228_PRE_PLL_POWER_DOWN; in inno_hdmi_phy_rk3228_clk_is_prepared()
551 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_rk3228_clk_prepare() local
553 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0); in inno_hdmi_phy_rk3228_clk_prepare()
559 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_rk3228_clk_unprepare() local
561 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, in inno_hdmi_phy_rk3228_clk_unprepare()
569 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_rk3228_clk_recalc_rate() local
574 nd = inno_read(inno, 0xe2) & RK3228_PRE_PLL_PRE_DIV_MASK; in inno_hdmi_phy_rk3228_clk_recalc_rate()
575 nf = (inno_read(inno, 0xe2) & RK3228_PRE_PLL_FB_DIV_8_MASK) << 1; in inno_hdmi_phy_rk3228_clk_recalc_rate()
576 nf |= inno_read(inno, 0xe3); in inno_hdmi_phy_rk3228_clk_recalc_rate()
579 if (inno_read(inno, 0xe2) & RK3228_PCLK_VCO_DIV_5_MASK) { in inno_hdmi_phy_rk3228_clk_recalc_rate()
582 no_a = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_A_MASK; in inno_hdmi_phy_rk3228_clk_recalc_rate()
585 no_b = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_B_MASK; in inno_hdmi_phy_rk3228_clk_recalc_rate()
588 no_d = inno_read(inno, 0xe5) & RK3228_PRE_PLL_PCLK_DIV_D_MASK; in inno_hdmi_phy_rk3228_clk_recalc_rate()
593 inno->pixclock = vco; in inno_hdmi_phy_rk3228_clk_recalc_rate()
595 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); in inno_hdmi_phy_rk3228_clk_recalc_rate()
622 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_rk3228_clk_set_rate() local
624 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); in inno_hdmi_phy_rk3228_clk_set_rate()
628 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", in inno_hdmi_phy_rk3228_clk_set_rate()
631 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); in inno_hdmi_phy_rk3228_clk_set_rate()
636 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, in inno_hdmi_phy_rk3228_clk_set_rate()
639 inno_update_bits(inno, 0xe2, RK3228_PRE_PLL_FB_DIV_8_MASK | in inno_hdmi_phy_rk3228_clk_set_rate()
645 inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_clk_set_rate()
646 inno_update_bits(inno, 0xe4, RK3228_PRE_PLL_PCLK_DIV_B_MASK | in inno_hdmi_phy_rk3228_clk_set_rate()
650 inno_update_bits(inno, 0xe5, RK3228_PRE_PLL_PCLK_DIV_C_MASK | in inno_hdmi_phy_rk3228_clk_set_rate()
654 inno_update_bits(inno, 0xe6, RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK | in inno_hdmi_phy_rk3228_clk_set_rate()
662 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0); in inno_hdmi_phy_rk3228_clk_set_rate()
665 ret = inno_poll(inno, 0xe8, v, v & RK3228_PRE_PLL_LOCK_STATUS, in inno_hdmi_phy_rk3228_clk_set_rate()
668 dev_err(inno->dev, "Pre-PLL locking failed\n"); in inno_hdmi_phy_rk3228_clk_set_rate()
672 inno->pixclock = rate; in inno_hdmi_phy_rk3228_clk_set_rate()
688 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_rk3328_clk_is_prepared() local
691 status = inno_read(inno, 0xa0) & RK3328_PRE_PLL_POWER_DOWN; in inno_hdmi_phy_rk3328_clk_is_prepared()
697 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_rk3328_clk_prepare() local
699 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0); in inno_hdmi_phy_rk3328_clk_prepare()
705 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_rk3328_clk_unprepare() local
707 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, in inno_hdmi_phy_rk3328_clk_unprepare()
715 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_rk3328_clk_recalc_rate() local
721 nd = inno_read(inno, 0xa1) & RK3328_PRE_PLL_PRE_DIV_MASK; in inno_hdmi_phy_rk3328_clk_recalc_rate()
722 nf = ((inno_read(inno, 0xa2) & RK3328_PRE_PLL_FB_DIV_11_8_MASK) << 8); in inno_hdmi_phy_rk3328_clk_recalc_rate()
723 nf |= inno_read(inno, 0xa3); in inno_hdmi_phy_rk3328_clk_recalc_rate()
726 if (!(inno_read(inno, 0xa2) & RK3328_PRE_PLL_FRAC_DIV_DISABLE)) { in inno_hdmi_phy_rk3328_clk_recalc_rate()
727 frac = inno_read(inno, 0xd3) | in inno_hdmi_phy_rk3328_clk_recalc_rate()
728 (inno_read(inno, 0xd2) << 8) | in inno_hdmi_phy_rk3328_clk_recalc_rate()
729 (inno_read(inno, 0xd1) << 16); in inno_hdmi_phy_rk3328_clk_recalc_rate()
733 if (inno_read(inno, 0xa0) & RK3328_PCLK_VCO_DIV_5_MASK) { in inno_hdmi_phy_rk3328_clk_recalc_rate()
736 no_a = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_A_MASK; in inno_hdmi_phy_rk3328_clk_recalc_rate()
737 no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK; in inno_hdmi_phy_rk3328_clk_recalc_rate()
740 no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK; in inno_hdmi_phy_rk3328_clk_recalc_rate()
743 no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK; in inno_hdmi_phy_rk3328_clk_recalc_rate()
748 inno->pixclock = vco; in inno_hdmi_phy_rk3328_clk_recalc_rate()
749 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); in inno_hdmi_phy_rk3328_clk_recalc_rate()
776 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); in inno_hdmi_phy_rk3328_clk_set_rate() local
778 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate); in inno_hdmi_phy_rk3328_clk_set_rate()
782 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", in inno_hdmi_phy_rk3328_clk_set_rate()
785 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); in inno_hdmi_phy_rk3328_clk_set_rate()
789 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, in inno_hdmi_phy_rk3328_clk_set_rate()
793 inno_update_bits(inno, 0xa0, RK3228_PCLK_VCO_DIV_5_MASK, in inno_hdmi_phy_rk3328_clk_set_rate()
795 inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3328_clk_set_rate()
800 inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); in inno_hdmi_phy_rk3328_clk_set_rate()
801 inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
802 inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) | in inno_hdmi_phy_rk3328_clk_set_rate()
804 inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | in inno_hdmi_phy_rk3328_clk_set_rate()
806 inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | in inno_hdmi_phy_rk3328_clk_set_rate()
809 inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
810 inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
811 inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
813 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0); in inno_hdmi_phy_rk3328_clk_set_rate()
816 ret = inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS, in inno_hdmi_phy_rk3328_clk_set_rate()
819 dev_err(inno->dev, "Pre-PLL locking failed\n"); in inno_hdmi_phy_rk3328_clk_set_rate()
823 inno->pixclock = rate; in inno_hdmi_phy_rk3328_clk_set_rate()
837 static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno) in inno_hdmi_phy_clk_register() argument
839 struct device *dev = inno->dev; in inno_hdmi_phy_clk_register()
845 parent_name = __clk_get_name(inno->refoclk); in inno_hdmi_phy_clk_register()
851 init.ops = inno->plat_data->clk_ops; in inno_hdmi_phy_clk_register()
856 inno->hw.init = &init; in inno_hdmi_phy_clk_register()
858 inno->phyclk = devm_clk_register(dev, &inno->hw); in inno_hdmi_phy_clk_register()
859 if (IS_ERR(inno->phyclk)) { in inno_hdmi_phy_clk_register()
860 ret = PTR_ERR(inno->phyclk); in inno_hdmi_phy_clk_register()
865 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->phyclk); in inno_hdmi_phy_clk_register()
874 static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3228_init() argument
880 inno_write(inno, 0x01, RK3228_BYPASS_RXSENSE_EN | in inno_hdmi_phy_rk3228_init()
883 inno_update_bits(inno, 0x02, RK3228_BYPASS_PDATA_EN, in inno_hdmi_phy_rk3228_init()
887 inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL, in inno_hdmi_phy_rk3228_init()
890 inno->chip_version = 1; in inno_hdmi_phy_rk3228_init()
896 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3228_power_on() argument
903 inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE, in inno_hdmi_phy_rk3228_power_on()
905 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN | in inno_hdmi_phy_rk3228_power_on()
911 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_PRE_DIV_MASK, in inno_hdmi_phy_rk3228_power_on()
913 inno_update_bits(inno, 0xeb, RK3228_POST_PLL_FB_DIV_8_MASK, in inno_hdmi_phy_rk3228_power_on()
915 inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
918 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE, in inno_hdmi_phy_rk3228_power_on()
923 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE, in inno_hdmi_phy_rk3228_power_on()
925 inno_update_bits(inno, 0xeb, RK3228_POST_PLL_POST_DIV_MASK, in inno_hdmi_phy_rk3228_power_on()
930 inno_write(inno, 0xef + v, phy_cfg->regs[v]); in inno_hdmi_phy_rk3228_power_on()
932 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN | in inno_hdmi_phy_rk3228_power_on()
934 inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE, in inno_hdmi_phy_rk3228_power_on()
936 inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE, in inno_hdmi_phy_rk3228_power_on()
940 ret = inno_poll(inno, 0xeb, v, v & RK3228_POST_PLL_LOCK_STATUS, in inno_hdmi_phy_rk3228_power_on()
943 dev_err(inno->dev, "Post-PLL locking failed\n"); in inno_hdmi_phy_rk3228_power_on()
950 inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE, 0); in inno_hdmi_phy_rk3228_power_on()
954 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3228_power_off() argument
956 inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE, 0); in inno_hdmi_phy_rk3228_power_off()
957 inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE, 0); in inno_hdmi_phy_rk3228_power_off()
958 inno_update_bits(inno, 0xe0, RK3228_POST_PLL_POWER_DOWN, in inno_hdmi_phy_rk3228_power_off()
968 static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3328_init() argument
978 inno_write(inno, 0x01, RK3328_BYPASS_RXSENSE_EN | in inno_hdmi_phy_rk3328_init()
981 inno_write(inno, 0x02, RK3328_INT_POL_HIGH | RK3328_BYPASS_PDATA_EN | in inno_hdmi_phy_rk3328_init()
985 inno_write(inno, 0x05, 0); in inno_hdmi_phy_rk3328_init()
986 inno_write(inno, 0x07, 0); in inno_hdmi_phy_rk3328_init()
989 inno->chip_version = 1; in inno_hdmi_phy_rk3328_init()
990 cell = nvmem_cell_get(inno->dev, "cpu-version"); in inno_hdmi_phy_rk3328_init()
1004 inno->chip_version = efuse_buf[0] + 1; in inno_hdmi_phy_rk3328_init()
1011 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, in inno_hdmi_phy_rk3328_power_on() argument
1018 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0); in inno_hdmi_phy_rk3328_power_on()
1019 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN, in inno_hdmi_phy_rk3328_power_on()
1022 inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3328_power_on()
1024 inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS); in inno_hdmi_phy_rk3328_power_on()
1025 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | in inno_hdmi_phy_rk3328_power_on()
1030 inno_write(inno, 0xad, v); in inno_hdmi_phy_rk3328_power_on()
1031 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | in inno_hdmi_phy_rk3328_power_on()
1033 inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE | in inno_hdmi_phy_rk3328_power_on()
1038 inno_write(inno, 0xb5 + v, phy_cfg->regs[v]); in inno_hdmi_phy_rk3328_power_on()
1042 inno_update_bits(inno, 0xc8 + v, RK3328_ESD_DETECT_MASK, in inno_hdmi_phy_rk3328_power_on()
1047 v = clk_get_rate(inno->sysclk) / 100000; in inno_hdmi_phy_rk3328_power_on()
1048 inno_write(inno, 0xc5, RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(v) in inno_hdmi_phy_rk3328_power_on()
1050 inno_write(inno, 0xc6, RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(v)); in inno_hdmi_phy_rk3328_power_on()
1051 inno_write(inno, 0xc7, RK3328_TERM_RESISTOR_100); in inno_hdmi_phy_rk3328_power_on()
1052 inno_update_bits(inno, 0xc5, in inno_hdmi_phy_rk3328_power_on()
1055 inno_write(inno, 0xc5, RK3328_BYPASS_TERM_RESISTOR_CALIB); in inno_hdmi_phy_rk3328_power_on()
1059 inno_update_bits(inno, 0xc8, in inno_hdmi_phy_rk3328_power_on()
1066 inno_update_bits(inno, 0xc9 + v, in inno_hdmi_phy_rk3328_power_on()
1071 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN, 0); in inno_hdmi_phy_rk3328_power_on()
1072 inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE, in inno_hdmi_phy_rk3328_power_on()
1074 inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE, in inno_hdmi_phy_rk3328_power_on()
1078 ret = inno_poll(inno, 0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS, in inno_hdmi_phy_rk3328_power_on()
1081 dev_err(inno->dev, "Post-PLL locking failed\n"); in inno_hdmi_phy_rk3328_power_on()
1088 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN); in inno_hdmi_phy_rk3328_power_on()
1091 inno_write(inno, 0x05, RK3328_INT_TMDS_CLK(RK3328_INT_VSS_AGND_ESD_DET) in inno_hdmi_phy_rk3328_power_on()
1093 inno_write(inno, 0x07, RK3328_INT_TMDS_D1(RK3328_INT_VSS_AGND_ESD_DET) in inno_hdmi_phy_rk3328_power_on()
1098 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno) in inno_hdmi_phy_rk3328_power_off() argument
1100 inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE, 0); in inno_hdmi_phy_rk3328_power_off()
1101 inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE, 0); in inno_hdmi_phy_rk3328_power_off()
1102 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN, in inno_hdmi_phy_rk3328_power_off()
1106 inno_write(inno, 0x05, 0); in inno_hdmi_phy_rk3328_power_off()
1107 inno_write(inno, 0x07, 0); in inno_hdmi_phy_rk3328_power_off()
1137 struct inno_hdmi_phy *inno = data; in inno_hdmi_phy_action() local
1139 clk_disable_unprepare(inno->refpclk); in inno_hdmi_phy_action()
1140 clk_disable_unprepare(inno->sysclk); in inno_hdmi_phy_action()
1145 struct inno_hdmi_phy *inno; in inno_hdmi_phy_probe() local
1151 inno = devm_kzalloc(&pdev->dev, sizeof(*inno), GFP_KERNEL); in inno_hdmi_phy_probe()
1152 if (!inno) in inno_hdmi_phy_probe()
1155 inno->dev = &pdev->dev; in inno_hdmi_phy_probe()
1157 inno->plat_data = of_device_get_match_data(inno->dev); in inno_hdmi_phy_probe()
1158 if (!inno->plat_data || !inno->plat_data->ops) in inno_hdmi_phy_probe()
1162 regs = devm_ioremap_resource(inno->dev, res); in inno_hdmi_phy_probe()
1166 inno->sysclk = devm_clk_get(inno->dev, "sysclk"); in inno_hdmi_phy_probe()
1167 if (IS_ERR(inno->sysclk)) { in inno_hdmi_phy_probe()
1168 ret = PTR_ERR(inno->sysclk); in inno_hdmi_phy_probe()
1169 dev_err(inno->dev, "failed to get sysclk: %d\n", ret); in inno_hdmi_phy_probe()
1173 inno->refpclk = devm_clk_get(inno->dev, "refpclk"); in inno_hdmi_phy_probe()
1174 if (IS_ERR(inno->refpclk)) { in inno_hdmi_phy_probe()
1175 ret = PTR_ERR(inno->refpclk); in inno_hdmi_phy_probe()
1176 dev_err(inno->dev, "failed to get ref clock: %d\n", ret); in inno_hdmi_phy_probe()
1180 inno->refoclk = devm_clk_get(inno->dev, "refoclk"); in inno_hdmi_phy_probe()
1181 if (IS_ERR(inno->refoclk)) { in inno_hdmi_phy_probe()
1182 ret = PTR_ERR(inno->refoclk); in inno_hdmi_phy_probe()
1183 dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n", in inno_hdmi_phy_probe()
1188 ret = clk_prepare_enable(inno->sysclk); in inno_hdmi_phy_probe()
1190 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret); in inno_hdmi_phy_probe()
1198 ret = clk_prepare_enable(inno->refpclk); in inno_hdmi_phy_probe()
1200 dev_err(inno->dev, "failed to enable refpclk\n"); in inno_hdmi_phy_probe()
1201 clk_disable_unprepare(inno->sysclk); in inno_hdmi_phy_probe()
1205 ret = devm_add_action_or_reset(inno->dev, inno_hdmi_phy_action, in inno_hdmi_phy_probe()
1206 inno); in inno_hdmi_phy_probe()
1210 inno->regmap = devm_regmap_init_mmio(inno->dev, regs, in inno_hdmi_phy_probe()
1212 if (IS_ERR(inno->regmap)) in inno_hdmi_phy_probe()
1213 return PTR_ERR(inno->regmap); in inno_hdmi_phy_probe()
1216 inno->irq = platform_get_irq(pdev, 0); in inno_hdmi_phy_probe()
1217 if (inno->irq > 0) { in inno_hdmi_phy_probe()
1218 ret = devm_request_threaded_irq(inno->dev, inno->irq, in inno_hdmi_phy_probe()
1222 dev_name(inno->dev), inno); in inno_hdmi_phy_probe()
1227 inno->phy = devm_phy_create(inno->dev, NULL, &inno_hdmi_phy_ops); in inno_hdmi_phy_probe()
1228 if (IS_ERR(inno->phy)) { in inno_hdmi_phy_probe()
1229 dev_err(inno->dev, "failed to create HDMI PHY\n"); in inno_hdmi_phy_probe()
1230 return PTR_ERR(inno->phy); in inno_hdmi_phy_probe()
1233 phy_set_drvdata(inno->phy, inno); in inno_hdmi_phy_probe()
1234 phy_set_bus_width(inno->phy, 8); in inno_hdmi_phy_probe()
1236 if (inno->plat_data->ops->init) { in inno_hdmi_phy_probe()
1237 ret = inno->plat_data->ops->init(inno); in inno_hdmi_phy_probe()
1242 ret = inno_hdmi_phy_clk_register(inno); in inno_hdmi_phy_probe()
1246 phy_provider = devm_of_phy_provider_register(inno->dev, in inno_hdmi_phy_probe()