Lines Matching +full:m +full:- +full:phy
16 #include <linux/clk-provider.h>
24 #include <linux/nvmem-consumer.h>
26 #include <linux/phy/phy.h>
173 struct phy *phy; member
348 /* tmdsclk bias-clk bias-data voltage-clk voltage-data pre-emphasis-data */
378 regmap_write(inno->regmap, reg * 4, val); in inno_write()
385 regmap_read(inno->regmap, reg * 4, &val); in inno_read()
393 regmap_update_bits(inno->regmap, reg * 4, mask, val); in inno_update_bits()
398 int bus_width = phy_get_bus_width(inno->phy); in inno_hdmi_phy_get_tmdsclk()
432 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_hardirq()
456 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_irq()
472 static int inno_hdmi_phy_power_on(struct phy *phy) in inno_hdmi_phy_power_on() argument
474 struct inno_hdmi_phy *inno = phy_get_drvdata(phy); in inno_hdmi_phy_power_on()
476 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table; in inno_hdmi_phy_power_on()
477 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock); in inno_hdmi_phy_power_on()
480 if (inno->phy_cfg) in inno_hdmi_phy_power_on()
481 phy_cfg = inno->phy_cfg; in inno_hdmi_phy_power_on()
484 dev_err(inno->dev, "TMDS clock is zero!\n"); in inno_hdmi_phy_power_on()
485 return -EINVAL; in inno_hdmi_phy_power_on()
488 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3328 && in inno_hdmi_phy_power_on()
491 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 && in inno_hdmi_phy_power_on()
492 tmdsclock <= 33750000 && inno->efuse_flag) in inno_hdmi_phy_power_on()
494 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3528) in inno_hdmi_phy_power_on()
497 for (; cfg->tmdsclock != ~0UL; cfg++) in inno_hdmi_phy_power_on()
498 if (tmdsclock <= cfg->tmdsclock && in inno_hdmi_phy_power_on()
499 cfg->version & chipversion) in inno_hdmi_phy_power_on()
502 for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++) in inno_hdmi_phy_power_on()
503 if (tmdsclock <= phy_cfg->tmdsclock) in inno_hdmi_phy_power_on()
506 if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL) in inno_hdmi_phy_power_on()
507 return -EINVAL; in inno_hdmi_phy_power_on()
509 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); in inno_hdmi_phy_power_on()
510 inno_hdmi_phy_clk_set_rate(&inno->hw, inno->pixclock, 0); in inno_hdmi_phy_power_on()
512 if (inno->plat_data->ops->power_on) in inno_hdmi_phy_power_on()
513 return inno->plat_data->ops->power_on(inno, cfg, phy_cfg); in inno_hdmi_phy_power_on()
515 return -EINVAL; in inno_hdmi_phy_power_on()
518 static int inno_hdmi_phy_power_off(struct phy *phy) in inno_hdmi_phy_power_off() argument
520 struct inno_hdmi_phy *inno = phy_get_drvdata(phy); in inno_hdmi_phy_power_off()
522 if (inno->plat_data->ops->power_off) in inno_hdmi_phy_power_off()
523 inno->plat_data->ops->power_off(inno); in inno_hdmi_phy_power_off()
525 inno->tmdsclock = 0; in inno_hdmi_phy_power_off()
526 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); in inno_hdmi_phy_power_off()
542 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_clk_is_prepared()
554 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_clk_prepare()
567 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228) in inno_hdmi_phy_clk_unprepare()
579 if (inno->plat_data->ops->recalc_rate) in inno_hdmi_phy_clk_recalc_rate()
580 return inno->plat_data->ops->recalc_rate(inno, parent_rate); in inno_hdmi_phy_clk_recalc_rate()
582 return inno->pixclock; in inno_hdmi_phy_clk_recalc_rate()
593 for (; cfg->pixclock != ~0UL; cfg++) in inno_hdmi_phy_clk_round_rate()
594 if (cfg->pixclock == rate) in inno_hdmi_phy_clk_round_rate()
598 if (cfg->pixclock > 600000000) in inno_hdmi_phy_clk_round_rate()
599 return -EINVAL; in inno_hdmi_phy_clk_round_rate()
602 * If there is no dts phy cfg table, use default phy cfg table. in inno_hdmi_phy_clk_round_rate()
606 if (!inno->phy_cfg) in inno_hdmi_phy_clk_round_rate()
607 return cfg->pixclock; in inno_hdmi_phy_clk_round_rate()
609 /* Check if tmds clock is out of dts phy config's range. */ in inno_hdmi_phy_clk_round_rate()
610 for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) { in inno_hdmi_phy_clk_round_rate()
611 if (inno->phy_cfg[i].tmdsclock >= tmdsclock) in inno_hdmi_phy_clk_round_rate()
615 if (inno->phy_cfg[i].tmdsclock == ~0UL) in inno_hdmi_phy_clk_round_rate()
616 return -EINVAL; in inno_hdmi_phy_clk_round_rate()
618 return cfg->pixclock; in inno_hdmi_phy_clk_round_rate()
628 dev_dbg(inno->dev, "%s rate %lu tmdsclk %u\n", in inno_hdmi_phy_clk_set_rate()
631 if (inno->tmdsclock == tmdsclock) in inno_hdmi_phy_clk_set_rate()
634 for (; cfg->pixclock != ~0UL; cfg++) in inno_hdmi_phy_clk_set_rate()
635 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock) in inno_hdmi_phy_clk_set_rate()
638 if (cfg->pixclock == ~0UL) { in inno_hdmi_phy_clk_set_rate()
639 dev_err(inno->dev, "unsupported rate %lu\n", rate); in inno_hdmi_phy_clk_set_rate()
640 return -EINVAL; in inno_hdmi_phy_clk_set_rate()
643 if (inno->plat_data->ops->pre_pll_update) in inno_hdmi_phy_clk_set_rate()
644 inno->plat_data->ops->pre_pll_update(inno, cfg); in inno_hdmi_phy_clk_set_rate()
646 inno->pixclock = rate; in inno_hdmi_phy_clk_set_rate()
647 inno->tmdsclock = tmdsclock; in inno_hdmi_phy_clk_set_rate()
663 struct device *dev = inno->dev; in inno_hdmi_phy_clk_register()
664 struct device_node *np = dev->of_node; in inno_hdmi_phy_clk_register()
671 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3528) in inno_hdmi_phy_clk_register()
672 clk_np = of_get_child_by_name(np, "clk-port"); in inno_hdmi_phy_clk_register()
692 of_property_read_string(clk_np, "clock-output-names", &init.name); in inno_hdmi_phy_clk_register()
694 inno->hw.init = &init; in inno_hdmi_phy_clk_register()
696 inno->pclk = devm_clk_register(dev, &inno->hw); in inno_hdmi_phy_clk_register()
697 if (IS_ERR(inno->pclk)) { in inno_hdmi_phy_clk_register()
698 ret = PTR_ERR(inno->pclk); in inno_hdmi_phy_clk_register()
703 ret = of_clk_add_provider(clk_np, of_clk_src_simple_get, inno->pclk); in inno_hdmi_phy_clk_register()
718 u32 m, v; in inno_hdmi_phy_rk3228_power_on() local
723 /* Power down Post-PLL */ in inno_hdmi_phy_rk3228_power_on()
727 /* Post-PLL update */ in inno_hdmi_phy_rk3228_power_on()
728 m = POST_PLL_PRE_DIV_MASK; in inno_hdmi_phy_rk3228_power_on()
729 v = POST_PLL_PRE_DIV(cfg->prediv); in inno_hdmi_phy_rk3228_power_on()
730 inno_update_bits(inno, 0xe9, m, v); in inno_hdmi_phy_rk3228_power_on()
732 m = POST_PLL_FB_DIV_8_MASK; in inno_hdmi_phy_rk3228_power_on()
733 v = POST_PLL_FB_DIV_8(cfg->fbdiv >> 8); in inno_hdmi_phy_rk3228_power_on()
734 inno_update_bits(inno, 0xeb, m, v); in inno_hdmi_phy_rk3228_power_on()
735 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
737 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3228_power_on()
738 /* Disable Post-PLL post divider */ in inno_hdmi_phy_rk3228_power_on()
739 m = POST_PLL_POST_DIV_EN_MASK; in inno_hdmi_phy_rk3228_power_on()
741 inno_update_bits(inno, 0xe9, m, v); in inno_hdmi_phy_rk3228_power_on()
743 /* Enable Post-PLL post divider */ in inno_hdmi_phy_rk3228_power_on()
744 m = POST_PLL_POST_DIV_EN_MASK; in inno_hdmi_phy_rk3228_power_on()
746 inno_update_bits(inno, 0xe9, m, v); in inno_hdmi_phy_rk3228_power_on()
748 m = POST_PLL_POST_DIV_MASK; in inno_hdmi_phy_rk3228_power_on()
749 v = POST_PLL_POST_DIV(cfg->postdiv / 2 - 1); in inno_hdmi_phy_rk3228_power_on()
750 inno_update_bits(inno, 0xeb, m, v); in inno_hdmi_phy_rk3228_power_on()
754 inno_write(inno, 0xef + v, phy_cfg->regs[v]); in inno_hdmi_phy_rk3228_power_on()
756 /* Power up Post-PLL */ in inno_hdmi_phy_rk3228_power_on()
770 dev_err(inno->dev, "Post-PLL unlock\n"); in inno_hdmi_phy_rk3228_power_on()
771 return -ETIMEDOUT; in inno_hdmi_phy_rk3228_power_on()
778 if (cfg->tmdsclock > 340000000) in inno_hdmi_phy_rk3228_power_on()
794 /* Post-PLL power down */ in inno_hdmi_phy_rk3228_power_off()
800 u32 m, v; in inno_hdmi_phy_rk3228_init() local
806 * Use phy internal register control in inno_hdmi_phy_rk3228_init()
809 m = BYPASS_RXSENSE_EN_MASK | BYPASS_PWRON_EN_MASK | in inno_hdmi_phy_rk3228_init()
812 inno_update_bits(inno, 0x01, m, v); in inno_hdmi_phy_rk3228_init()
817 * if phy had been set in uboot, one of them will be different. in inno_hdmi_phy_rk3228_init()
820 dev_info(inno->dev, "phy had been powered up\n"); in inno_hdmi_phy_rk3228_init()
821 inno->phy->power_count = 1; in inno_hdmi_phy_rk3228_init()
824 /* manual power down post-PLL */ in inno_hdmi_phy_rk3228_init()
829 cell = nvmem_cell_get(inno->dev, "hdmi_phy_flag"); in inno_hdmi_phy_rk3228_init()
831 dev_err(inno->dev, in inno_hdmi_phy_rk3228_init()
838 inno->efuse_flag = efuse_buf[0] ? true : false; in inno_hdmi_phy_rk3228_init()
847 u32 m, v; in inno_hdmi_phy_rk3228_pre_pll_update() local
849 /* Power down PRE-PLL */ in inno_hdmi_phy_rk3228_pre_pll_update()
852 m = PRE_PLL_FB_DIV_8_MASK | PCLK_VCO_DIV_5_MASK | PRE_PLL_PRE_DIV_MASK; in inno_hdmi_phy_rk3228_pre_pll_update()
853 v = PRE_PLL_FB_DIV_8(cfg->fbdiv >> 8) | in inno_hdmi_phy_rk3228_pre_pll_update()
854 PCLK_VCO_DIV_5(cfg->vco_div_5_en) | PRE_PLL_PRE_DIV(cfg->prediv); in inno_hdmi_phy_rk3228_pre_pll_update()
855 inno_update_bits(inno, 0xe2, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
857 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_pre_pll_update()
859 m = PRE_PLL_PCLK_DIV_B_MASK | PRE_PLL_PCLK_DIV_A_MASK; in inno_hdmi_phy_rk3228_pre_pll_update()
860 v = PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) | in inno_hdmi_phy_rk3228_pre_pll_update()
861 PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a); in inno_hdmi_phy_rk3228_pre_pll_update()
862 inno_update_bits(inno, 0xe4, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
864 m = PRE_PLL_PCLK_DIV_C_MASK | PRE_PLL_PCLK_DIV_D_MASK; in inno_hdmi_phy_rk3228_pre_pll_update()
865 v = PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) | in inno_hdmi_phy_rk3228_pre_pll_update()
866 PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d); in inno_hdmi_phy_rk3228_pre_pll_update()
867 inno_update_bits(inno, 0xe5, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
869 m = PRE_PLL_TMDSCLK_DIV_C_MASK | PRE_PLL_TMDSCLK_DIV_A_MASK | in inno_hdmi_phy_rk3228_pre_pll_update()
871 v = PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) | in inno_hdmi_phy_rk3228_pre_pll_update()
872 PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) | in inno_hdmi_phy_rk3228_pre_pll_update()
873 PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b); in inno_hdmi_phy_rk3228_pre_pll_update()
874 inno_update_bits(inno, 0xe6, m, v); in inno_hdmi_phy_rk3228_pre_pll_update()
876 /* Power up PRE-PLL */ in inno_hdmi_phy_rk3228_pre_pll_update()
879 /* Wait for Pre-PLL lock */ in inno_hdmi_phy_rk3228_pre_pll_update()
883 dev_err(inno->dev, "Pre-PLL unlock\n"); in inno_hdmi_phy_rk3228_pre_pll_update()
884 return -ETIMEDOUT; in inno_hdmi_phy_rk3228_pre_pll_update()
907 val = cfg->fbdiv & 0xff; in inno_hdmi_phy_rk3328_power_on()
909 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3328_power_on()
911 val = (cfg->fbdiv >> 8) | cfg->prediv; in inno_hdmi_phy_rk3328_power_on()
914 val = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3328_power_on()
916 val = (cfg->fbdiv >> 8) | cfg->prediv; in inno_hdmi_phy_rk3328_power_on()
922 inno_write(inno, 0xb5 + val, phy_cfg->regs[val]); in inno_hdmi_phy_rk3328_power_on()
925 * 00 - 340mV in inno_hdmi_phy_rk3328_power_on()
926 * 01 - 280mV in inno_hdmi_phy_rk3328_power_on()
927 * 10 - 260mV in inno_hdmi_phy_rk3328_power_on()
928 * 11 - 240mV in inno_hdmi_phy_rk3328_power_on()
936 if (phy_cfg->tmdsclock > 340000000) { in inno_hdmi_phy_rk3328_power_on()
938 val = clk_get_rate(inno->sysclk) / 100000; in inno_hdmi_phy_rk3328_power_on()
946 if (phy_cfg->tmdsclock > 165000000) in inno_hdmi_phy_rk3328_power_on()
956 do_div(temp, inno->tmdsclock); in inno_hdmi_phy_rk3328_power_on()
973 dev_err(inno->dev, "HDMI PHY Post PLL unlock\n"); in inno_hdmi_phy_rk3328_power_on()
974 return -ETIMEDOUT; in inno_hdmi_phy_rk3328_power_on()
976 if (phy_cfg->tmdsclock > 340000000) in inno_hdmi_phy_rk3328_power_on()
981 /* Enable PHY IRQ */ in inno_hdmi_phy_rk3328_power_on()
996 /* Disable PHY IRQ */ in inno_hdmi_phy_rk3328_power_off()
1004 * Use phy internal register control in inno_hdmi_phy_rk3328_init()
1011 * reg0xc8 default value is 0xc0, if phy had been set in uboot, in inno_hdmi_phy_rk3328_init()
1015 dev_info(inno->dev, "phy had been powered up\n"); in inno_hdmi_phy_rk3328_init()
1016 inno->phy->power_count = 1; in inno_hdmi_phy_rk3328_init()
1018 /* manual power down post-PLL */ in inno_hdmi_phy_rk3328_init()
1031 /* Configure pre-pll */ in inno_hdmi_phy_rk3328_pre_pll_update()
1032 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1); in inno_hdmi_phy_rk3328_pre_pll_update()
1033 inno_write(inno, 0xa1, cfg->prediv); in inno_hdmi_phy_rk3328_pre_pll_update()
1034 if (cfg->fracdiv) in inno_hdmi_phy_rk3328_pre_pll_update()
1035 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0; in inno_hdmi_phy_rk3328_pre_pll_update()
1037 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0; in inno_hdmi_phy_rk3328_pre_pll_update()
1039 inno_write(inno, 0xa3, cfg->fbdiv & 0xff); in inno_hdmi_phy_rk3328_pre_pll_update()
1040 val = (cfg->pclk_div_a & 0x1f) | in inno_hdmi_phy_rk3328_pre_pll_update()
1041 ((cfg->pclk_div_b & 3) << 5); in inno_hdmi_phy_rk3328_pre_pll_update()
1043 val = (cfg->pclk_div_d & 0x1f) | in inno_hdmi_phy_rk3328_pre_pll_update()
1044 ((cfg->pclk_div_c & 3) << 5); in inno_hdmi_phy_rk3328_pre_pll_update()
1046 val = ((cfg->tmds_div_a & 3) << 4) | in inno_hdmi_phy_rk3328_pre_pll_update()
1047 ((cfg->tmds_div_b & 3) << 2) | in inno_hdmi_phy_rk3328_pre_pll_update()
1048 (cfg->tmds_div_c & 3); in inno_hdmi_phy_rk3328_pre_pll_update()
1051 if (cfg->fracdiv) { in inno_hdmi_phy_rk3328_pre_pll_update()
1052 val = cfg->fracdiv & 0xff; in inno_hdmi_phy_rk3328_pre_pll_update()
1054 val = (cfg->fracdiv >> 8) & 0xff; in inno_hdmi_phy_rk3328_pre_pll_update()
1056 val = (cfg->fracdiv >> 16) & 0xff; in inno_hdmi_phy_rk3328_pre_pll_update()
1074 dev_err(inno->dev, "Pre-PLL unlock\n"); in inno_hdmi_phy_rk3328_pre_pll_update()
1075 return -ETIMEDOUT; in inno_hdmi_phy_rk3328_pre_pll_update()
1112 inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000; in inno_hdmi_rk3328_phy_pll_recalc_rate()
1114 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); in inno_hdmi_rk3328_phy_pll_recalc_rate()
1130 val = cfg->prediv; in inno_hdmi_phy_rk3528_power_on()
1133 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3528_power_on()
1137 val = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3528_power_on()
1142 val = cfg->fbdiv & 0xff; in inno_hdmi_phy_rk3528_power_on()
1144 val = (cfg->fbdiv >> 8) & BIT(0); in inno_hdmi_phy_rk3528_power_on()
1148 val = phy_cfg->regs[0] << 4 | phy_cfg->regs[1]; in inno_hdmi_phy_rk3528_power_on()
1152 val = phy_cfg->regs[1] << 4 | phy_cfg->regs[1]; in inno_hdmi_phy_rk3528_power_on()
1156 inno_write(inno, 0xb5, phy_cfg->regs[2]); in inno_hdmi_phy_rk3528_power_on()
1157 inno_write(inno, 0xb6, phy_cfg->regs[3]); in inno_hdmi_phy_rk3528_power_on()
1158 inno_write(inno, 0xb7, phy_cfg->regs[3]); in inno_hdmi_phy_rk3528_power_on()
1159 inno_write(inno, 0xb8, phy_cfg->regs[3]); in inno_hdmi_phy_rk3528_power_on()
1161 /* pre-emphasis */ in inno_hdmi_phy_rk3528_power_on()
1162 inno_write(inno, 0xbb, phy_cfg->regs[4]); in inno_hdmi_phy_rk3528_power_on()
1163 inno_write(inno, 0xbc, phy_cfg->regs[4]); in inno_hdmi_phy_rk3528_power_on()
1164 inno_write(inno, 0xbd, phy_cfg->regs[4]); in inno_hdmi_phy_rk3528_power_on()
1180 dev_err(inno->dev, "HDMI PHY Post PLL unlock\n"); in inno_hdmi_phy_rk3528_power_on()
1181 return -ETIMEDOUT; in inno_hdmi_phy_rk3528_power_on()
1185 if (phy_cfg->tmdsclock > 340000000) { in inno_hdmi_phy_rk3528_power_on()
1203 do_div(temp, inno->tmdsclock); in inno_hdmi_phy_rk3528_power_on()
1213 if (phy_cfg->tmdsclock > 340000000) in inno_hdmi_phy_rk3528_power_on()
1219 /* Enable PHY IRQ */ in inno_hdmi_phy_rk3528_power_on()
1239 /* Disable PHY IRQ */ in inno_hdmi_phy_rk3528_power_off()
1247 * Use phy internal register control in inno_hdmi_phy_rk3528_init()
1252 /* if phy had been set in uboot, pll is locked */ in inno_hdmi_phy_rk3528_init()
1254 dev_info(inno->dev, "phy had been powered up\n"); in inno_hdmi_phy_rk3528_init()
1255 inno->phy->power_count = 1; in inno_hdmi_phy_rk3528_init()
1257 /* manual power down post-PLL */ in inno_hdmi_phy_rk3528_init()
1273 /* Configure pre-pll */ in inno_hdmi_phy_rk3528_pre_pll_update()
1274 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1); in inno_hdmi_phy_rk3528_pre_pll_update()
1275 inno_write(inno, 0xa1, cfg->prediv); in inno_hdmi_phy_rk3528_pre_pll_update()
1276 if (cfg->fracdiv) in inno_hdmi_phy_rk3528_pre_pll_update()
1277 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0; in inno_hdmi_phy_rk3528_pre_pll_update()
1279 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0; in inno_hdmi_phy_rk3528_pre_pll_update()
1281 inno_write(inno, 0xa3, cfg->fbdiv & 0xff); in inno_hdmi_phy_rk3528_pre_pll_update()
1282 val = (cfg->pclk_div_a & 0x1f) | in inno_hdmi_phy_rk3528_pre_pll_update()
1283 ((cfg->pclk_div_b & 3) << 5); in inno_hdmi_phy_rk3528_pre_pll_update()
1285 val = (cfg->pclk_div_d & 0x1f) | in inno_hdmi_phy_rk3528_pre_pll_update()
1286 ((cfg->pclk_div_c & 3) << 5); in inno_hdmi_phy_rk3528_pre_pll_update()
1288 val = ((cfg->tmds_div_a & 3) << 4) | in inno_hdmi_phy_rk3528_pre_pll_update()
1289 ((cfg->tmds_div_b & 3) << 2) | in inno_hdmi_phy_rk3528_pre_pll_update()
1290 (cfg->tmds_div_c & 3); in inno_hdmi_phy_rk3528_pre_pll_update()
1293 if (cfg->fracdiv) { in inno_hdmi_phy_rk3528_pre_pll_update()
1294 val = cfg->fracdiv & 0xff; in inno_hdmi_phy_rk3528_pre_pll_update()
1296 val = (cfg->fracdiv >> 8) & 0xff; in inno_hdmi_phy_rk3528_pre_pll_update()
1298 val = (cfg->fracdiv >> 16) & 0xff; in inno_hdmi_phy_rk3528_pre_pll_update()
1313 dev_err(inno->dev, "Pre-PLL unlock\n"); in inno_hdmi_phy_rk3528_pre_pll_update()
1314 return -ETIMEDOUT; in inno_hdmi_phy_rk3528_pre_pll_update()
1351 inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000; in inno_hdmi_rk3528_phy_pll_recalc_rate()
1353 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); in inno_hdmi_rk3528_phy_pll_recalc_rate()
1385 inno->pixclock = vco; in inno_hdmi_rk3228_phy_pll_recalc_rate()
1387 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); in inno_hdmi_rk3228_phy_pll_recalc_rate()
1389 return inno->pixclock; in inno_hdmi_rk3228_phy_pll_recalc_rate()
1435 { .compatible = "rockchip,rk3228-hdmi-phy",
1438 { .compatible = "rockchip,rk3328-hdmi-phy",
1441 { .compatible = "rockchip,rk3528-hdmi-phy",
1471 * The last set of phy cfg is used to indicate whether in inno_hdmi_update_phy_table()
1472 * there is no more phy cfg data. in inno_hdmi_update_phy_table()
1485 struct device *dev = &pdev->dev; in inno_hdmi_phy_probe()
1486 struct device_node *np = dev->of_node; in inno_hdmi_phy_probe()
1497 return -ENOMEM; in inno_hdmi_phy_probe()
1499 inno->dev = dev; in inno_hdmi_phy_probe()
1501 match = of_match_node(inno_hdmi_phy_of_match, pdev->dev.of_node); in inno_hdmi_phy_probe()
1502 inno->plat_data = (struct inno_hdmi_phy_drv_data *)match->data; in inno_hdmi_phy_probe()
1503 if (!inno->plat_data || !inno->plat_data->ops) in inno_hdmi_phy_probe()
1504 return -EINVAL; in inno_hdmi_phy_probe()
1511 inno->sysclk = devm_clk_get(inno->dev, "sysclk"); in inno_hdmi_phy_probe()
1512 if (IS_ERR(inno->sysclk)) { in inno_hdmi_phy_probe()
1513 ret = PTR_ERR(inno->sysclk); in inno_hdmi_phy_probe()
1514 dev_err(inno->dev, "Unable to get inno phy sysclk: %d\n", ret); in inno_hdmi_phy_probe()
1517 ret = clk_prepare_enable(inno->sysclk); in inno_hdmi_phy_probe()
1519 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret); in inno_hdmi_phy_probe()
1523 inno->regmap = devm_regmap_init_mmio(dev, regs, in inno_hdmi_phy_probe()
1525 if (IS_ERR(inno->regmap)) { in inno_hdmi_phy_probe()
1526 ret = PTR_ERR(inno->regmap); in inno_hdmi_phy_probe()
1531 inno->phy = devm_phy_create(dev, NULL, &inno_hdmi_phy_ops); in inno_hdmi_phy_probe()
1532 if (IS_ERR(inno->phy)) { in inno_hdmi_phy_probe()
1533 dev_err(dev, "failed to create HDMI PHY\n"); in inno_hdmi_phy_probe()
1534 ret = PTR_ERR(inno->phy); in inno_hdmi_phy_probe()
1538 if (of_get_property(np, "rockchip,phy-table", &val)) { in inno_hdmi_phy_probe()
1540 dev_err(dev, "Invalid phy cfg table format!\n"); in inno_hdmi_phy_probe()
1541 ret = -EINVAL; in inno_hdmi_phy_probe()
1547 dev_err(dev, "kmalloc phy table failed\n"); in inno_hdmi_phy_probe()
1548 ret = -ENOMEM; in inno_hdmi_phy_probe()
1553 /* Effective phy cfg data and the end of phy cfg table */ in inno_hdmi_phy_probe()
1554 inno->phy_cfg = devm_kzalloc(dev, val + PHY_TAB_LEN, in inno_hdmi_phy_probe()
1556 if (!inno->phy_cfg) { in inno_hdmi_phy_probe()
1558 ret = -ENOMEM; in inno_hdmi_phy_probe()
1561 of_property_read_u32_array(np, "rockchip,phy-table", in inno_hdmi_phy_probe()
1564 inno->phy_cfg, in inno_hdmi_phy_probe()
1572 dev_dbg(dev, "use default hdmi phy table\n"); in inno_hdmi_phy_probe()
1575 phy_set_drvdata(inno->phy, inno); in inno_hdmi_phy_probe()
1576 phy_set_bus_width(inno->phy, 8); in inno_hdmi_phy_probe()
1580 dev_err(dev, "failed to register PHY provider\n"); in inno_hdmi_phy_probe()
1585 if (inno->plat_data->ops->init) in inno_hdmi_phy_probe()
1586 inno->plat_data->ops->init(inno); in inno_hdmi_phy_probe()
1592 inno->irq = platform_get_irq(pdev, 0); in inno_hdmi_phy_probe()
1593 if (inno->irq > 0) { in inno_hdmi_phy_probe()
1594 ret = devm_request_threaded_irq(inno->dev, inno->irq, in inno_hdmi_phy_probe()
1597 dev_name(inno->dev), inno); in inno_hdmi_phy_probe()
1605 of_clk_del_provider(pdev->dev.of_node); in inno_hdmi_phy_probe()
1607 clk_disable_unprepare(inno->sysclk); in inno_hdmi_phy_probe()
1615 of_clk_del_provider(pdev->dev.of_node); in inno_hdmi_phy_remove()
1616 clk_disable_unprepare(inno->sysclk); in inno_hdmi_phy_remove()
1624 .name = "inno-hdmi-phy",
1631 MODULE_DESCRIPTION("Innosilion HDMI 2.0 Transmitter PHY Driver");