73 	const struct rockchip_combphy_grfcfg grfcfg;  member
145 	if (param_read(priv->usb_pcie_grf, &priv->cfg->grfcfg.u3_port_num, 0))  in u3phy_mode_show()
158 	    param_read(priv->usb_pcie_grf, &priv->cfg->grfcfg.u3_port_num, 0)) {  in u3phy_mode_store()
164 			    &priv->cfg->grfcfg.pipe_l0rxterm_sel, false);  in u3phy_mode_store()
167 			    &priv->cfg->grfcfg.u3_port_num, true);  in u3phy_mode_store()
170 			    &priv->cfg->grfcfg.u3_port_disable, false);  in u3phy_mode_store()
174 			      &priv->cfg->grfcfg.u3_port_num, 1)) {  in u3phy_mode_store()
181 			    &priv->cfg->grfcfg.pipe_l0rxterm_set, false);  in u3phy_mode_store()
183 			    &priv->cfg->grfcfg.pipe_l0rxterm_sel, true);  in u3phy_mode_store()
186 			    &priv->cfg->grfcfg.u3_port_num, false);  in u3phy_mode_store()
189 			    &priv->cfg->grfcfg.u3_port_disable, true);  in u3phy_mode_store()
220 	const struct rockchip_combphy_grfcfg *grfcfg;  in rockchip_combphy_pll_lock()  local
223 	grfcfg = &priv->cfg->grfcfg;  in rockchip_combphy_pll_lock()
224 	mask = GENMASK(grfcfg->pipe_pll_lock.bitend,  in rockchip_combphy_pll_lock()
225 		       grfcfg->pipe_pll_lock.bitstart);  in rockchip_combphy_pll_lock()
227 	regmap_read(priv->combphy_grf, grfcfg->pipe_pll_lock.offset, &val);  in rockchip_combphy_pll_lock()
228 	val = (val & mask) >> grfcfg->pipe_pll_lock.bitstart;  in rockchip_combphy_pll_lock()
235 	const struct rockchip_combphy_grfcfg *grfcfg;  in rockchip_combphy_is_ready()  local
238 	grfcfg = &priv->cfg->grfcfg;  in rockchip_combphy_is_ready()
239 	mask = GENMASK(grfcfg->pipe_status_l0.bitend,  in rockchip_combphy_is_ready()
240 		       grfcfg->pipe_status_l0.bitstart);  in rockchip_combphy_is_ready()
242 	regmap_read(priv->combphy_grf, grfcfg->pipe_status_l0.offset, &val);  in rockchip_combphy_is_ready()
243 	val = (val & mask) >> grfcfg->pipe_status_l0.bitstart;  in rockchip_combphy_is_ready()
250 	const struct rockchip_combphy_grfcfg *grfcfg;  in phy_pcie_init()  local
254 	grfcfg = &priv->cfg->grfcfg;  in phy_pcie_init()
268 	param_write(priv->combphy_grf, &grfcfg->pipe_l0rxterm_set, true);  in phy_pcie_init()
270 	param_write(priv->combphy_grf, &grfcfg->pipe_l1rxterm_set, true);  in phy_pcie_init()
272 	param_write(priv->combphy_grf, &grfcfg->pipe_l0rxterm_sel, true);  in phy_pcie_init()
274 	param_write(priv->combphy_grf, &grfcfg->pipe_l1rxterm_sel, true);  in phy_pcie_init()
276 	param_write(priv->combphy_grf, &grfcfg->pipe_txrx_sel, false);  in phy_pcie_init()
288 					val == grfcfg->pipe_pll_lock.enable,  in phy_pcie_init()
302 	const struct rockchip_combphy_grfcfg *grfcfg;  in phy_u3_init()  local
306 	grfcfg = &priv->cfg->grfcfg;  in phy_u3_init()
326 	param_write(priv->combphy_grf, &grfcfg->pipe_l1_set, true);  in phy_u3_init()
327 	param_write(priv->combphy_grf, &grfcfg->pipe_l1_sel, true);  in phy_u3_init()
330 	param_write(priv->combphy_grf, &grfcfg->pipe_txrx_set, true);  in phy_u3_init()
331 	param_write(priv->combphy_grf, &grfcfg->pipe_txrx_sel, true);  in phy_u3_init()
334 	param_write(priv->combphy_grf, &grfcfg->pipe_clk_set, true);  in phy_u3_init()
335 	param_write(priv->combphy_grf, &grfcfg->pipe_clk_sel, true);  in phy_u3_init()
338 	param_write(priv->combphy_grf, &grfcfg->pipe_rate_set, true);  in phy_u3_init()
339 	param_write(priv->combphy_grf, &grfcfg->pipe_rate_sel, true);  in phy_u3_init()
342 	param_write(priv->combphy_grf, &grfcfg->pipe_mode_set, true);  in phy_u3_init()
343 	param_write(priv->combphy_grf, &grfcfg->pipe_mode_sel, true);  in phy_u3_init()
346 	param_write(priv->combphy_grf, &grfcfg->pipe_width_set, true);  in phy_u3_init()
347 	param_write(priv->combphy_grf, &grfcfg->pipe_width_sel, true);  in phy_u3_init()
350 	param_write(priv->combphy_grf, &grfcfg->pipe_usb3_sel, true);  in phy_u3_init()
361 					val == grfcfg->pipe_pll_lock.enable,  in phy_u3_init()
372 					val == grfcfg->pipe_status_l0.enable,  in phy_u3_init()
462 	const struct rockchip_combphy_grfcfg *grfcfg;  in rockchip_combphy_power_on()  local
467 	grfcfg = &priv->cfg->grfcfg;  in rockchip_combphy_power_on()
474 		param_write(priv->combphy_grf, &grfcfg->pipe_l0rxelec_set,  in rockchip_combphy_power_on()
482 			       &grfcfg->pipe_l0pd_sel, 0))  in rockchip_combphy_power_on()
486 		param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_p3, false);  in rockchip_combphy_power_on()
493 		param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_sel, false);  in rockchip_combphy_power_on()
504 	const struct rockchip_combphy_grfcfg *grfcfg;  in rockchip_combphy_power_off()  local
509 	grfcfg = &priv->cfg->grfcfg;  in rockchip_combphy_power_off()
518 			       &grfcfg->pipe_l0pd_sel, 1) &&  in rockchip_combphy_power_off()
520 			       &grfcfg->pipe_l0pd_p3, 3))  in rockchip_combphy_power_off()
524 		param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_p3, false);  in rockchip_combphy_power_off()
525 		param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_sel, true);  in rockchip_combphy_power_off()
529 		param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_p3, true);  in rockchip_combphy_power_off()
537 		param_write(priv->combphy_grf, &grfcfg->pipe_l0rxelec_set,  in rockchip_combphy_power_off()
970 	.grfcfg	= {