Lines Matching +full:en +full:- +full:usb
1 // SPDX-License-Identifier: GPL-2.0
20 #include <dt-bindings/phy/phy.h>
76 bool en);
97 return "otg-rst"; in get_reset_name()
99 return "combphy-por"; in get_reset_name()
101 return "combphy-apb"; in get_reset_name()
103 return "combphy-pipe"; in get_reset_name()
117 ret = regmap_read(base, reg->offset, &orig); in param_read()
121 mask = GENMASK(reg->bitend, reg->bitstart); in param_read()
122 tmp = (orig & mask) >> reg->bitstart; in param_read()
128 const struct combphy_reg *reg, bool en) in param_write() argument
132 tmp = en ? reg->enable : reg->disable; in param_write()
133 mask = GENMASK(reg->bitend, reg->bitstart); in param_write()
134 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in param_write()
136 return regmap_write(base, reg->offset, val); in param_write()
145 if (param_read(priv->usb_pcie_grf, &priv->cfg->grfcfg.u3_port_num, 0)) in u3phy_mode_show()
158 param_read(priv->usb_pcie_grf, &priv->cfg->grfcfg.u3_port_num, 0)) { in u3phy_mode_store()
160 * Enable USB 3.0 rx termination, need to select in u3phy_mode_store()
161 * pipe_l0_rxtermination from USB 3.0 controller. in u3phy_mode_store()
163 param_write(priv->combphy_grf, in u3phy_mode_store()
164 &priv->cfg->grfcfg.pipe_l0rxterm_sel, false); in u3phy_mode_store()
165 /* Set xHCI USB 3.0 port number to 1 */ in u3phy_mode_store()
166 param_write(priv->usb_pcie_grf, in u3phy_mode_store()
167 &priv->cfg->grfcfg.u3_port_num, true); in u3phy_mode_store()
168 /* Enable xHCI USB 3.0 port */ in u3phy_mode_store()
169 param_write(priv->usb_pcie_grf, in u3phy_mode_store()
170 &priv->cfg->grfcfg.u3_port_disable, false); in u3phy_mode_store()
171 dev_info(priv->dev, "Set usb3.0 and usb2.0 mode successfully\n"); in u3phy_mode_store()
173 param_read(priv->usb_pcie_grf, in u3phy_mode_store()
174 &priv->cfg->grfcfg.u3_port_num, 1)) { in u3phy_mode_store()
176 * Disable USB 3.0 rx termination, need to select in u3phy_mode_store()
180 param_write(priv->combphy_grf, in u3phy_mode_store()
181 &priv->cfg->grfcfg.pipe_l0rxterm_set, false); in u3phy_mode_store()
182 param_write(priv->combphy_grf, in u3phy_mode_store()
183 &priv->cfg->grfcfg.pipe_l0rxterm_sel, true); in u3phy_mode_store()
184 /* Set xHCI USB 3.0 port number to 0 */ in u3phy_mode_store()
185 param_write(priv->usb_pcie_grf, in u3phy_mode_store()
186 &priv->cfg->grfcfg.u3_port_num, false); in u3phy_mode_store()
187 /* Disable xHCI USB 3.0 port */ in u3phy_mode_store()
188 param_write(priv->usb_pcie_grf, in u3phy_mode_store()
189 &priv->cfg->grfcfg.u3_port_disable, true); in u3phy_mode_store()
192 * Don't disable the USB 3.0 PIPE pclk here(set reg in u3phy_mode_store()
193 * pipe_usb3_sel to false), because USB 3.0 PHY depend in u3phy_mode_store()
195 * the USB 3.0 PHY when use USB 3.0 mode, in order to in u3phy_mode_store()
198 dev_info(priv->dev, "Set usb2.0 only mode successfully\n"); in u3phy_mode_store()
200 dev_info(priv->dev, "Same or illegal mode\n"); in u3phy_mode_store()
223 grfcfg = &priv->cfg->grfcfg; in rockchip_combphy_pll_lock()
224 mask = GENMASK(grfcfg->pipe_pll_lock.bitend, in rockchip_combphy_pll_lock()
225 grfcfg->pipe_pll_lock.bitstart); in rockchip_combphy_pll_lock()
227 regmap_read(priv->combphy_grf, grfcfg->pipe_pll_lock.offset, &val); in rockchip_combphy_pll_lock()
228 val = (val & mask) >> grfcfg->pipe_pll_lock.bitstart; in rockchip_combphy_pll_lock()
238 grfcfg = &priv->cfg->grfcfg; in rockchip_combphy_is_ready()
239 mask = GENMASK(grfcfg->pipe_status_l0.bitend, in rockchip_combphy_is_ready()
240 grfcfg->pipe_status_l0.bitstart); in rockchip_combphy_is_ready()
242 regmap_read(priv->combphy_grf, grfcfg->pipe_status_l0.offset, &val); in rockchip_combphy_is_ready()
243 val = (val & mask) >> grfcfg->pipe_status_l0.bitstart; in rockchip_combphy_is_ready()
254 grfcfg = &priv->cfg->grfcfg; in phy_pcie_init()
257 reset_control_assert(priv->rsts[PHY_POR_RSTN]); in phy_pcie_init()
258 reset_control_assert(priv->rsts[PHY_APB_RSTN]); in phy_pcie_init()
259 reset_control_assert(priv->rsts[PHY_PIPE_RSTN]); in phy_pcie_init()
261 reset_control_deassert(priv->rsts[PHY_POR_RSTN]); in phy_pcie_init()
264 reset_control_deassert(priv->rsts[PHY_APB_RSTN]); in phy_pcie_init()
268 param_write(priv->combphy_grf, &grfcfg->pipe_l0rxterm_set, true); in phy_pcie_init()
270 param_write(priv->combphy_grf, &grfcfg->pipe_l1rxterm_set, true); in phy_pcie_init()
272 param_write(priv->combphy_grf, &grfcfg->pipe_l0rxterm_sel, true); in phy_pcie_init()
274 param_write(priv->combphy_grf, &grfcfg->pipe_l1rxterm_sel, true); in phy_pcie_init()
276 param_write(priv->combphy_grf, &grfcfg->pipe_txrx_sel, false); in phy_pcie_init()
279 if (priv->cfg->combphy_cfg) { in phy_pcie_init()
280 ret = priv->cfg->combphy_cfg(priv); in phy_pcie_init()
288 val == grfcfg->pipe_pll_lock.enable, in phy_pcie_init()
291 dev_err(priv->dev, "wait phy PLL lock timeout\n"); in phy_pcie_init()
295 reset_control_deassert(priv->rsts[PHY_PIPE_RSTN]); in phy_pcie_init()
306 grfcfg = &priv->cfg->grfcfg; in phy_u3_init()
309 reset_control_assert(priv->rsts[OTG_RSTN]); in phy_u3_init()
311 reset_control_deassert(priv->rsts[PHY_POR_RSTN]); in phy_u3_init()
315 reset_control_deassert(priv->rsts[PHY_APB_RSTN]); in phy_u3_init()
326 param_write(priv->combphy_grf, &grfcfg->pipe_l1_set, true); in phy_u3_init()
327 param_write(priv->combphy_grf, &grfcfg->pipe_l1_sel, true); in phy_u3_init()
330 param_write(priv->combphy_grf, &grfcfg->pipe_txrx_set, true); in phy_u3_init()
331 param_write(priv->combphy_grf, &grfcfg->pipe_txrx_sel, true); in phy_u3_init()
334 param_write(priv->combphy_grf, &grfcfg->pipe_clk_set, true); in phy_u3_init()
335 param_write(priv->combphy_grf, &grfcfg->pipe_clk_sel, true); in phy_u3_init()
338 param_write(priv->combphy_grf, &grfcfg->pipe_rate_set, true); in phy_u3_init()
339 param_write(priv->combphy_grf, &grfcfg->pipe_rate_sel, true); in phy_u3_init()
342 param_write(priv->combphy_grf, &grfcfg->pipe_mode_set, true); in phy_u3_init()
343 param_write(priv->combphy_grf, &grfcfg->pipe_mode_sel, true); in phy_u3_init()
346 param_write(priv->combphy_grf, &grfcfg->pipe_width_set, true); in phy_u3_init()
347 param_write(priv->combphy_grf, &grfcfg->pipe_width_sel, true); in phy_u3_init()
350 param_write(priv->combphy_grf, &grfcfg->pipe_usb3_sel, true); in phy_u3_init()
352 if (priv->cfg->combphy_cfg) { in phy_u3_init()
353 ret = priv->cfg->combphy_cfg(priv); in phy_u3_init()
361 val == grfcfg->pipe_pll_lock.enable, in phy_u3_init()
364 dev_err(priv->dev, "wait phy PLL lock timeout\n"); in phy_u3_init()
368 reset_control_deassert(priv->rsts[PHY_PIPE_RSTN]); in phy_u3_init()
372 val == grfcfg->pipe_status_l0.enable, in phy_u3_init()
375 dev_err(priv->dev, "wait phy status lane0 ready timeout\n"); in phy_u3_init()
379 reset_control_deassert(priv->rsts[OTG_RSTN]); in phy_u3_init()
389 if (priv->phy_initialized) in rockchip_combphy_set_phy_type()
392 switch (priv->phy_type) { in rockchip_combphy_set_phy_type()
402 ret = sysfs_create_group(&priv->dev->kobj, in rockchip_combphy_set_phy_type()
406 dev_err(priv->dev, "incompatible PHY type\n"); in rockchip_combphy_set_phy_type()
407 return -EINVAL; in rockchip_combphy_set_phy_type()
418 ret = clk_prepare_enable(priv->ref_clk); in rockchip_combphy_init()
420 dev_err(priv->dev, "failed to enable ref_clk\n"); in rockchip_combphy_init()
426 dev_err(priv->dev, "failed to set phy type\n"); in rockchip_combphy_init()
430 priv->phy_initialized = true; in rockchip_combphy_init()
446 clk_disable_unprepare(priv->ref_clk); in rockchip_combphy_exit()
449 if (priv->phy_type == PHY_TYPE_PCIE) { in rockchip_combphy_exit()
450 reset_control_assert(priv->rsts[PHY_GRF_P_RSTN]); in rockchip_combphy_exit()
452 reset_control_deassert(priv->rsts[PHY_GRF_P_RSTN]); in rockchip_combphy_exit()
453 priv->phy_initialized = false; in rockchip_combphy_exit()
464 if (!priv->phy_suspended) in rockchip_combphy_power_on()
467 grfcfg = &priv->cfg->grfcfg; in rockchip_combphy_power_on()
469 if (priv->phy_type == PHY_TYPE_USB3) { in rockchip_combphy_power_on()
470 if (priv->cfg->combphy_low_power_ctrl) in rockchip_combphy_power_on()
471 priv->cfg->combphy_low_power_ctrl(priv, false); in rockchip_combphy_power_on()
474 param_write(priv->combphy_grf, &grfcfg->pipe_l0rxelec_set, in rockchip_combphy_power_on()
479 * controlled by USB 3.0 controller. in rockchip_combphy_power_on()
481 if (param_read(priv->combphy_grf, in rockchip_combphy_power_on()
482 &grfcfg->pipe_l0pd_sel, 0)) in rockchip_combphy_power_on()
486 param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_p3, false); in rockchip_combphy_power_on()
491 * by USB 3.0 controller. in rockchip_combphy_power_on()
493 param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_sel, false); in rockchip_combphy_power_on()
497 priv->phy_suspended = false; in rockchip_combphy_power_on()
506 if (priv->phy_suspended) in rockchip_combphy_power_off()
509 grfcfg = &priv->cfg->grfcfg; in rockchip_combphy_power_off()
511 if (priv->phy_type == PHY_TYPE_USB3 || in rockchip_combphy_power_off()
512 priv->phy_type == PHY_TYPE_PCIE) { in rockchip_combphy_power_off()
517 if (param_read(priv->combphy_grf, in rockchip_combphy_power_off()
518 &grfcfg->pipe_l0pd_sel, 1) && in rockchip_combphy_power_off()
519 param_read(priv->combphy_grf, in rockchip_combphy_power_off()
520 &grfcfg->pipe_l0pd_p3, 3)) in rockchip_combphy_power_off()
524 param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_p3, false); in rockchip_combphy_power_off()
525 param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_sel, true); in rockchip_combphy_power_off()
529 param_write(priv->combphy_grf, &grfcfg->pipe_l0pd_p3, true); in rockchip_combphy_power_off()
537 param_write(priv->combphy_grf, &grfcfg->pipe_l0rxelec_set, in rockchip_combphy_power_off()
540 if (priv->cfg->combphy_low_power_ctrl) in rockchip_combphy_power_off()
541 priv->cfg->combphy_low_power_ctrl(priv, true); in rockchip_combphy_power_off()
545 priv->phy_suspended = true; in rockchip_combphy_power_off()
554 if (priv->phy_type != PHY_TYPE_PCIE) in rockchip_combphy_set_mode()
555 return -EINVAL; in rockchip_combphy_set_mode()
557 reg = readl(priv->mmio + 0x21a8); in rockchip_combphy_set_mode()
564 return -EINVAL; in rockchip_combphy_set_mode()
566 writel(reg, priv->mmio + 0x21a8); in rockchip_combphy_set_mode()
584 if (args->args_count < 1) { in rockchip_combphy_xlate()
586 return ERR_PTR(-EINVAL); in rockchip_combphy_xlate()
589 if (priv->phy_type != PHY_NONE && priv->phy_type != args->args[0]) { in rockchip_combphy_xlate()
591 args->args[0], priv->phy_type); in rockchip_combphy_xlate()
592 return ERR_PTR(-ENODEV); in rockchip_combphy_xlate()
595 priv->phy_type = args->args[0]; in rockchip_combphy_xlate()
597 if (priv->phy_type < PHY_TYPE_SATA || priv->phy_type > PHY_TYPE_USB3) { in rockchip_combphy_xlate()
599 return ERR_PTR(-EINVAL); in rockchip_combphy_xlate()
602 return priv->phy; in rockchip_combphy_xlate()
610 priv->combphy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, in rockchip_combphy_parse_dt()
612 if (IS_ERR(priv->combphy_grf)) { in rockchip_combphy_parse_dt()
614 return PTR_ERR(priv->combphy_grf); in rockchip_combphy_parse_dt()
617 priv->usb_pcie_grf = syscon_regmap_lookup_by_phandle(dev->of_node, in rockchip_combphy_parse_dt()
619 if (IS_ERR(priv->usb_pcie_grf)) { in rockchip_combphy_parse_dt()
621 return PTR_ERR(priv->usb_pcie_grf); in rockchip_combphy_parse_dt()
624 priv->ref_clk = devm_clk_get(dev, "refclk"); in rockchip_combphy_parse_dt()
625 if (IS_ERR(priv->ref_clk)) { in rockchip_combphy_parse_dt()
627 return PTR_ERR(priv->ref_clk); in rockchip_combphy_parse_dt()
631 priv->rsts[i] = devm_reset_control_get(dev, get_reset_name(i)); in rockchip_combphy_parse_dt()
632 if (IS_ERR(priv->rsts[i])) { in rockchip_combphy_parse_dt()
635 priv->rsts[i] = NULL; in rockchip_combphy_parse_dt()
645 struct device *dev = &pdev->dev; in rockchip_combphy_probe()
654 return -EINVAL; in rockchip_combphy_probe()
659 return -ENOMEM; in rockchip_combphy_probe()
662 priv->mmio = devm_ioremap_resource(dev, res); in rockchip_combphy_probe()
663 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
664 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
674 reset_control_assert(priv->rsts[PHY_POR_RSTN]); in rockchip_combphy_probe()
675 reset_control_assert(priv->rsts[PHY_APB_RSTN]); in rockchip_combphy_probe()
676 reset_control_assert(priv->rsts[PHY_PIPE_RSTN]); in rockchip_combphy_probe()
678 priv->phy_type = PHY_NONE; in rockchip_combphy_probe()
679 priv->dev = dev; in rockchip_combphy_probe()
680 priv->cfg = phy_cfg; in rockchip_combphy_probe()
681 priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops); in rockchip_combphy_probe()
682 if (IS_ERR(priv->phy)) { in rockchip_combphy_probe()
684 return PTR_ERR(priv->phy); in rockchip_combphy_probe()
688 phy_set_drvdata(priv->phy, priv); in rockchip_combphy_probe()
699 if (priv->phy_type == PHY_TYPE_USB3 && priv->phy_initialized) in rockchip_combphy_remove()
700 sysfs_remove_group(&priv->dev->kobj, in rockchip_combphy_remove()
712 rate = clk_get_rate(priv->ref_clk); in rk1808_combphy_cfg()
723 writel(0x00, priv->mmio + 0x2118); in rk1808_combphy_cfg()
724 writel(0x64, priv->mmio + 0x211c); in rk1808_combphy_cfg()
725 writel(0x01, priv->mmio + 0x2020); in rk1808_combphy_cfg()
726 writel(0x64, priv->mmio + 0x2028); in rk1808_combphy_cfg()
727 writel(0x21, priv->mmio + 0x2030); in rk1808_combphy_cfg()
729 if (priv->phy_type == PHY_TYPE_PCIE) { in rk1808_combphy_cfg()
730 writel(0x1, priv->mmio + 0x3020); in rk1808_combphy_cfg()
731 writel(0x64, priv->mmio + 0x3028); in rk1808_combphy_cfg()
732 writel(0x21, priv->mmio + 0x3030); in rk1808_combphy_cfg()
737 writel(0x00, priv->mmio + 0x2118); in rk1808_combphy_cfg()
738 writel(0x32, priv->mmio + 0x211c); in rk1808_combphy_cfg()
739 writel(0x01, priv->mmio + 0x2020); in rk1808_combphy_cfg()
740 writel(0x32, priv->mmio + 0x2028); in rk1808_combphy_cfg()
741 writel(0x21, priv->mmio + 0x2030); in rk1808_combphy_cfg()
744 dev_err(priv->dev, "Unsupported rate: %lu\n", rate); in rk1808_combphy_cfg()
745 return -EINVAL; in rk1808_combphy_cfg()
748 if (priv->phy_type == PHY_TYPE_PCIE) { in rk1808_combphy_cfg()
750 writel(0x08400000, priv->mmio + 0x0); in rk1808_combphy_cfg()
751 writel(0x03030000, priv->mmio + 0x8); in rk1808_combphy_cfg()
754 writel(0x20, priv->mmio + 0x20ac); in rk1808_combphy_cfg()
755 writel(0x12, priv->mmio + 0x20c8); in rk1808_combphy_cfg()
756 writel(0x76, priv->mmio + 0x2150); in rk1808_combphy_cfg()
759 writel(0x20, priv->mmio + 0x30ac); in rk1808_combphy_cfg()
760 writel(0x12, priv->mmio + 0x30c8); in rk1808_combphy_cfg()
761 writel(0x76, priv->mmio + 0x3150); in rk1808_combphy_cfg()
763 writel(0x0, priv->mmio + 0x21a4); in rk1808_combphy_cfg()
764 writel(0x0, priv->mmio + 0x21a8); in rk1808_combphy_cfg()
765 writel(0xb, priv->mmio + 0x21ec); in rk1808_combphy_cfg()
768 writel(0x02, priv->mmio + 0x45c0); in rk1808_combphy_cfg()
769 writel(0x83, priv->mmio + 0x45c4); in rk1808_combphy_cfg()
770 writel(0x03, priv->mmio + 0x45c8); in rk1808_combphy_cfg()
771 writel(0x43, priv->mmio + 0x45cc); in rk1808_combphy_cfg()
772 writel(0x00, priv->mmio + 0x45d0); in rk1808_combphy_cfg()
773 writel(0xbc, priv->mmio + 0x45d4); in rk1808_combphy_cfg()
775 /* Boost pre-emphasis */ in rk1808_combphy_cfg()
776 writel(0xaa, priv->mmio + 0x21b8); in rk1808_combphy_cfg()
777 writel(0xaa, priv->mmio + 0x31b8); in rk1808_combphy_cfg()
778 } else if (priv->phy_type == PHY_TYPE_USB3) { in rk1808_combphy_cfg()
784 writel(0x09, priv->mmio + 0x3148); in rk1808_combphy_cfg()
787 writel(0x01, priv->mmio + 0x21cc); in rk1808_combphy_cfg()
790 writel(0x08, priv->mmio + 0x30c4); in rk1808_combphy_cfg()
791 writel(0x08, priv->mmio + 0x20f4); in rk1808_combphy_cfg()
794 writel(0x12, priv->mmio + 0x3150); in rk1808_combphy_cfg()
797 writel(0x04, priv->mmio + 0x3080); in rk1808_combphy_cfg()
800 writel(0x1d, priv->mmio + 0x3090); in rk1808_combphy_cfg()
803 writel(0x50, priv->mmio + 0x21c4); in rk1808_combphy_cfg()
804 writel(0x10, priv->mmio + 0x2050); in rk1808_combphy_cfg()
807 writel(0x81, priv->mmio + 0x31a8); in rk1808_combphy_cfg()
810 writel(0x00, priv->mmio + 0x31e8); in rk1808_combphy_cfg()
813 writel(0x08, priv->mmio + 0x30c0); in rk1808_combphy_cfg()
816 writel(0x20, priv->mmio + 0x20ac); in rk1808_combphy_cfg()
822 reg = readl(priv->mmio + 0x2108); in rk1808_combphy_cfg()
824 writel(reg, priv->mmio + 0x2108); in rk1808_combphy_cfg()
829 reg = readl(priv->mmio + 0x2108); in rk1808_combphy_cfg()
831 writel(reg, priv->mmio + 0x2108); in rk1808_combphy_cfg()
835 dev_warn(priv->dev, in rk1808_combphy_cfg()
842 reg = readl(priv->mmio + 0x2120); in rk1808_combphy_cfg()
844 writel(reg, priv->mmio + 0x2120); in rk1808_combphy_cfg()
846 reg = readl(priv->mmio + 0x2000); in rk1808_combphy_cfg()
848 writel(reg, priv->mmio + 0x2000); in rk1808_combphy_cfg()
857 reg = readl(priv->mmio + 0x21b8); in rk1808_combphy_cfg()
859 writel(reg, priv->mmio + 0x21b8); in rk1808_combphy_cfg()
865 reg = readl(priv->mmio + 0x20c8); in rk1808_combphy_cfg()
867 writel(reg, priv->mmio + 0x20c8); in rk1808_combphy_cfg()
868 reg = readl(priv->mmio + 0x2150); in rk1808_combphy_cfg()
870 writel(reg, priv->mmio + 0x2150); in rk1808_combphy_cfg()
872 dev_err(priv->dev, "failed to cfg incompatible PHY type\n"); in rk1808_combphy_cfg()
873 return -EINVAL; in rk1808_combphy_cfg()
880 bool en) in rk1808_combphy_low_power_control() argument
882 if (priv->phy_type != PHY_TYPE_USB3) { in rk1808_combphy_low_power_control()
884 writel(0x08400840, priv->mmio + 0x0); in rk1808_combphy_low_power_control()
885 writel(0x03030303, priv->mmio + 0x8); in rk1808_combphy_low_power_control()
888 writel(0x36, priv->mmio + 0x2150); in rk1808_combphy_low_power_control()
889 writel(0x36, priv->mmio + 0x3150); in rk1808_combphy_low_power_control()
890 writel(0x02, priv->mmio + 0x21e8); in rk1808_combphy_low_power_control()
891 writel(0x02, priv->mmio + 0x31e8); in rk1808_combphy_low_power_control()
892 writel(0x0c, priv->mmio + 0x2080); in rk1808_combphy_low_power_control()
893 writel(0x0c, priv->mmio + 0x3080); in rk1808_combphy_low_power_control()
894 writel(0x08, priv->mmio + 0x20c0); in rk1808_combphy_low_power_control()
895 writel(0x08, priv->mmio + 0x30c0); in rk1808_combphy_low_power_control()
896 writel(0x08, priv->mmio + 0x2058); in rk1808_combphy_low_power_control()
898 writel(0x10, priv->mmio + 0x2044); in rk1808_combphy_low_power_control()
899 writel(0x10, priv->mmio + 0x21a8); in rk1808_combphy_low_power_control()
900 writel(0x10, priv->mmio + 0x31a8); in rk1808_combphy_low_power_control()
901 writel(0x08, priv->mmio + 0x2058); in rk1808_combphy_low_power_control()
902 writel(0x08, priv->mmio + 0x3058); in rk1808_combphy_low_power_control()
903 writel(0x40, priv->mmio + 0x205c); in rk1808_combphy_low_power_control()
904 writel(0x40, priv->mmio + 0x305c); in rk1808_combphy_low_power_control()
905 writel(0x08, priv->mmio + 0x2184); in rk1808_combphy_low_power_control()
906 writel(0x08, priv->mmio + 0x3184); in rk1808_combphy_low_power_control()
907 writel(0x00, priv->mmio + 0x2150); in rk1808_combphy_low_power_control()
908 writel(0x00, priv->mmio + 0x3150); in rk1808_combphy_low_power_control()
909 writel(0x10, priv->mmio + 0x20e0); in rk1808_combphy_low_power_control()
910 writel(0x00, priv->mmio + 0x21e8); in rk1808_combphy_low_power_control()
911 writel(0x00, priv->mmio + 0x31e8); in rk1808_combphy_low_power_control()
916 if (en) { in rk1808_combphy_low_power_control()
918 writel(0x36, priv->mmio + 0x2150); in rk1808_combphy_low_power_control()
921 writel(0x02, priv->mmio + 0x21e8); in rk1808_combphy_low_power_control()
924 writel(0x0c, priv->mmio + 0x2080); in rk1808_combphy_low_power_control()
927 writel(0x08, priv->mmio + 0x20c0); in rk1808_combphy_low_power_control()
930 writel(0x10, priv->mmio + 0x2044); in rk1808_combphy_low_power_control()
933 writel(0x08, priv->mmio + 0x2058); in rk1808_combphy_low_power_control()
936 writel(0x91, priv->mmio + 0x21a8); in rk1808_combphy_low_power_control()
939 writel(0x91, priv->mmio + 0x31a8); in rk1808_combphy_low_power_control()
942 writel(0x76, priv->mmio + 0x2150); in rk1808_combphy_low_power_control()
945 writel(0x02, priv->mmio + 0x21e8); in rk1808_combphy_low_power_control()
948 writel(0x08, priv->mmio + 0x2080); in rk1808_combphy_low_power_control()
951 writel(0x18, priv->mmio + 0x20c0); in rk1808_combphy_low_power_control()
954 writel(0x00, priv->mmio + 0x2044); in rk1808_combphy_low_power_control()
957 writel(0x28, priv->mmio + 0x2058); in rk1808_combphy_low_power_control()
960 writel(0x01, priv->mmio + 0x21a8); in rk1808_combphy_low_power_control()
963 writel(0x81, priv->mmio + 0x31a8); in rk1808_combphy_low_power_control()
1004 .compatible = "rockchip,rk1808-combphy",
1016 .name = "rockchip-combphy",
1022 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");