420 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)  in qusb2_phy_override_phy_params()  argument
422 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_override_phy_params()
423 	struct override_params *or = &qphy->overrides;  in qusb2_phy_override_phy_params()
426 		qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,  in qusb2_phy_override_phy_params()
431 		qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,  in qusb2_phy_override_phy_params()
436 		qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,  in qusb2_phy_override_phy_params()
441 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],  in qusb2_phy_override_phy_params()
446 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],  in qusb2_phy_override_phy_params()
453 			qusb2_setbits(qphy->base,  in qusb2_phy_override_phy_params()
457 			qusb2_clrbits(qphy->base,  in qusb2_phy_override_phy_params()
463 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],  in qusb2_phy_override_phy_params()
473 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)  in qusb2_phy_set_tune2_param()  argument
475 	struct device *dev = &qphy->phy->dev;  in qusb2_phy_set_tune2_param()
476 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_set_tune2_param()
480 	if (!qphy->cell)  in qusb2_phy_set_tune2_param()
490 	val = nvmem_cell_read(qphy->cell, NULL);  in qusb2_phy_set_tune2_param()
504 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],  in qusb2_phy_set_tune2_param()
507 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],  in qusb2_phy_set_tune2_param()
514 	struct qusb2_phy *qphy = phy_get_drvdata(phy);  in qusb2_phy_set_mode()  local
516 	qphy->mode = mode;  in qusb2_phy_set_mode()
523 	struct qusb2_phy *qphy = dev_get_drvdata(dev);  in qusb2_phy_runtime_suspend()  local
524 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_runtime_suspend()
527 	dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);  in qusb2_phy_runtime_suspend()
529 	if (!qphy->phy_initialized) {  in qusb2_phy_runtime_suspend()
541 	switch (qphy->mode) {  in qusb2_phy_runtime_suspend()
559 	writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);  in qusb2_phy_runtime_suspend()
563 		qusb2_setbits(qphy->base,  in qusb2_phy_runtime_suspend()
570 	if (qphy->mode != PHY_MODE_INVALID) {  in qusb2_phy_runtime_suspend()
571 		qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],  in qusb2_phy_runtime_suspend()
574 		qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],  in qusb2_phy_runtime_suspend()
578 	if (!qphy->has_se_clk_scheme)  in qusb2_phy_runtime_suspend()
579 		clk_disable_unprepare(qphy->ref_clk);  in qusb2_phy_runtime_suspend()
581 	clk_disable_unprepare(qphy->cfg_ahb_clk);  in qusb2_phy_runtime_suspend()
582 	clk_disable_unprepare(qphy->iface_clk);  in qusb2_phy_runtime_suspend()
589 	struct qusb2_phy *qphy = dev_get_drvdata(dev);  in qusb2_phy_runtime_resume()  local
590 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_runtime_resume()
593 	dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);  in qusb2_phy_runtime_resume()
595 	if (!qphy->phy_initialized) {  in qusb2_phy_runtime_resume()
600 	ret = clk_prepare_enable(qphy->iface_clk);  in qusb2_phy_runtime_resume()
606 	ret = clk_prepare_enable(qphy->cfg_ahb_clk);  in qusb2_phy_runtime_resume()
612 	if (!qphy->has_se_clk_scheme) {  in qusb2_phy_runtime_resume()
613 		ret = clk_prepare_enable(qphy->ref_clk);  in qusb2_phy_runtime_resume()
620 	writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);  in qusb2_phy_runtime_resume()
624 		qusb2_clrbits(qphy->base,  in qusb2_phy_runtime_resume()
632 	clk_disable_unprepare(qphy->cfg_ahb_clk);  in qusb2_phy_runtime_resume()
634 	clk_disable_unprepare(qphy->iface_clk);  in qusb2_phy_runtime_resume()
641 	struct qusb2_phy *qphy = phy_get_drvdata(phy);  in qusb2_phy_init()  local
642 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_init()
650 	ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);  in qusb2_phy_init()
654 	ret = clk_prepare_enable(qphy->iface_clk);  in qusb2_phy_init()
661 	ret = clk_prepare_enable(qphy->cfg_ahb_clk);  in qusb2_phy_init()
668 	ret = reset_control_assert(qphy->phy_reset);  in qusb2_phy_init()
677 	ret = reset_control_deassert(qphy->phy_reset);  in qusb2_phy_init()
684 	qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],  in qusb2_phy_init()
685 		      qphy->cfg->disable_ctrl);  in qusb2_phy_init()
689 		val = readl(qphy->base + QUSB2PHY_PLL_TEST);  in qusb2_phy_init()
692 	qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,  in qusb2_phy_init()
696 	qusb2_phy_override_phy_params(qphy);  in qusb2_phy_init()
699 	qusb2_phy_set_tune2_param(qphy);  in qusb2_phy_init()
702 	qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],  in qusb2_phy_init()
709 	qphy->has_se_clk_scheme = true;  in qusb2_phy_init()
716 	if (qphy->tcsr) {  in qusb2_phy_init()
717 		ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,  in qusb2_phy_init()
728 			qphy->has_se_clk_scheme = false;  in qusb2_phy_init()
735 	if (!qphy->has_se_clk_scheme) {  in qusb2_phy_init()
736 		ret = clk_prepare_enable(qphy->ref_clk);  in qusb2_phy_init()
745 		if (!qphy->has_se_clk_scheme)  in qusb2_phy_init()
750 		writel(val, qphy->base + QUSB2PHY_PLL_TEST);  in qusb2_phy_init()
753 		readl(qphy->base + QUSB2PHY_PLL_TEST);  in qusb2_phy_init()
759 	val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);  in qusb2_phy_init()
766 	qphy->phy_initialized = true;  in qusb2_phy_init()
771 	if (!qphy->has_se_clk_scheme)  in qusb2_phy_init()
772 		clk_disable_unprepare(qphy->ref_clk);  in qusb2_phy_init()
774 	reset_control_assert(qphy->phy_reset);  in qusb2_phy_init()
776 	clk_disable_unprepare(qphy->cfg_ahb_clk);  in qusb2_phy_init()
778 	clk_disable_unprepare(qphy->iface_clk);  in qusb2_phy_init()
780 	regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);  in qusb2_phy_init()
787 	struct qusb2_phy *qphy = phy_get_drvdata(phy);  in qusb2_phy_exit()  local
790 	qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],  in qusb2_phy_exit()
791 		      qphy->cfg->disable_ctrl);  in qusb2_phy_exit()
793 	if (!qphy->has_se_clk_scheme)  in qusb2_phy_exit()
794 		clk_disable_unprepare(qphy->ref_clk);  in qusb2_phy_exit()
796 	reset_control_assert(qphy->phy_reset);  in qusb2_phy_exit()
798 	clk_disable_unprepare(qphy->cfg_ahb_clk);  in qusb2_phy_exit()
799 	clk_disable_unprepare(qphy->iface_clk);  in qusb2_phy_exit()
801 	regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);  in qusb2_phy_exit()
803 	qphy->phy_initialized = false;  in qusb2_phy_exit()
848 	struct qusb2_phy *qphy;  in qusb2_phy_probe()  local
857 	qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);  in qusb2_phy_probe()
858 	if (!qphy)  in qusb2_phy_probe()
860 	or = &qphy->overrides;  in qusb2_phy_probe()
863 	qphy->base = devm_ioremap_resource(dev, res);  in qusb2_phy_probe()
864 	if (IS_ERR(qphy->base))  in qusb2_phy_probe()
865 		return PTR_ERR(qphy->base);  in qusb2_phy_probe()
867 	qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");  in qusb2_phy_probe()
868 	if (IS_ERR(qphy->cfg_ahb_clk)) {  in qusb2_phy_probe()
869 		ret = PTR_ERR(qphy->cfg_ahb_clk);  in qusb2_phy_probe()
875 	qphy->ref_clk = devm_clk_get(dev, "ref");  in qusb2_phy_probe()
876 	if (IS_ERR(qphy->ref_clk)) {  in qusb2_phy_probe()
877 		ret = PTR_ERR(qphy->ref_clk);  in qusb2_phy_probe()
883 	qphy->iface_clk = devm_clk_get_optional(dev, "iface");  in qusb2_phy_probe()
884 	if (IS_ERR(qphy->iface_clk))  in qusb2_phy_probe()
885 		return PTR_ERR(qphy->iface_clk);  in qusb2_phy_probe()
887 	qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);  in qusb2_phy_probe()
888 	if (IS_ERR(qphy->phy_reset)) {  in qusb2_phy_probe()
890 		return PTR_ERR(qphy->phy_reset);  in qusb2_phy_probe()
893 	num = ARRAY_SIZE(qphy->vregs);  in qusb2_phy_probe()
895 		qphy->vregs[i].supply = qusb2_phy_vreg_names[i];  in qusb2_phy_probe()
897 	ret = devm_regulator_bulk_get(dev, num, qphy->vregs);  in qusb2_phy_probe()
906 	qphy->cfg = of_device_get_match_data(dev);  in qusb2_phy_probe()
908 	qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,  in qusb2_phy_probe()
910 	if (IS_ERR(qphy->tcsr)) {  in qusb2_phy_probe()
912 		qphy->tcsr = NULL;  in qusb2_phy_probe()
915 	qphy->cell = devm_nvmem_cell_get(dev, NULL);  in qusb2_phy_probe()
916 	if (IS_ERR(qphy->cell)) {  in qusb2_phy_probe()
917 		if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)  in qusb2_phy_probe()
919 		qphy->cell = NULL;  in qusb2_phy_probe()
980 	qphy->phy = generic_phy;  in qusb2_phy_probe()
982 	dev_set_drvdata(dev, qphy);  in qusb2_phy_probe()
983 	phy_set_drvdata(generic_phy, qphy);  in qusb2_phy_probe()