122 	/* PCS registers */
1834 	/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1888 	/* true, if PCS block has no separate SW_RESET register */
1905  * @pcs: iomapped memory space for lane's pcs
1921 	void __iomem *pcs;  member
2689 	       qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);  in qcom_qmp_phy_dp_aux_init()
2696 	writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);  in qcom_qmp_phy_dp_aux_init()
2702 	       qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);  in qcom_qmp_phy_dp_aux_init()
2710 	writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0);  in qcom_qmp_phy_dp_aux_init()
2711 	writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);  in qcom_qmp_phy_dp_aux_init()
2712 	writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);  in qcom_qmp_phy_dp_aux_init()
2713 	writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3);  in qcom_qmp_phy_dp_aux_init()
2714 	writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4);  in qcom_qmp_phy_dp_aux_init()
2715 	writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5);  in qcom_qmp_phy_dp_aux_init()
2716 	writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6);  in qcom_qmp_phy_dp_aux_init()
2717 	writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7);  in qcom_qmp_phy_dp_aux_init()
2718 	writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8);  in qcom_qmp_phy_dp_aux_init()
2719 	writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9);  in qcom_qmp_phy_dp_aux_init()
2725 	       qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);  in qcom_qmp_phy_dp_aux_init()
2821 	 *	writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);  in qcom_qmp_phy_configure_dp_phy()
2824 	writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);  in qcom_qmp_phy_configure_dp_phy()
2826 	writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);  in qcom_qmp_phy_configure_dp_phy()
2827 	writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);  in qcom_qmp_phy_configure_dp_phy()
2828 	writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);  in qcom_qmp_phy_configure_dp_phy()
2851 	writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);  in qcom_qmp_phy_configure_dp_phy()
2856 	writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);  in qcom_qmp_phy_configure_dp_phy()
2857 	writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);  in qcom_qmp_phy_configure_dp_phy()
2858 	writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG);  in qcom_qmp_phy_configure_dp_phy()
2859 	writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);  in qcom_qmp_phy_configure_dp_phy()
2860 	writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG);  in qcom_qmp_phy_configure_dp_phy()
2871 	writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);  in qcom_qmp_phy_configure_dp_phy()
2873 	if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,  in qcom_qmp_phy_configure_dp_phy()
2880 	writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG);  in qcom_qmp_phy_configure_dp_phy()
2882 	writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);  in qcom_qmp_phy_configure_dp_phy()
2884 	return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,  in qcom_qmp_phy_configure_dp_phy()
2905 	writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);  in qcom_qmp_dp_phy_calibrate()
2915 	void __iomem *pcs = qphy->pcs;  in qcom_qmp_phy_com_init()  local
2970 		/* bring both QMP USB and QMP DP PHYs PCS block out of reset */  in qcom_qmp_phy_com_init()
2984 			qphy_setbits(pcs,  in qcom_qmp_phy_com_init()
2988 			qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,  in qcom_qmp_phy_com_init()
3094 	void __iomem *pcs = qphy->pcs;  in qcom_qmp_phy_power_on()  local
3117 	/* Tx, Rx, and PCS configurations */  in qcom_qmp_phy_power_on()
3140 		qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);  in qcom_qmp_phy_power_on()
3154 		qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);  in qcom_qmp_phy_power_on()
3162 			qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);  in qcom_qmp_phy_power_on()
3164 		qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);  in qcom_qmp_phy_power_on()
3167 			status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];  in qcom_qmp_phy_power_on()
3171 			status = pcs + cfg->regs[QPHY_PCS_STATUS];  in qcom_qmp_phy_power_on()
3203 		writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);  in qcom_qmp_phy_power_off()
3207 			qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);  in qcom_qmp_phy_power_off()
3210 		qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);  in qcom_qmp_phy_power_off()
3214 			qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],  in qcom_qmp_phy_power_off()
3217 			qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,  in qcom_qmp_phy_power_off()
3276 	void __iomem *pcs = qphy->pcs;  in qcom_qmp_phy_enable_autonomous_mode()  local
3287 	qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);  in qcom_qmp_phy_enable_autonomous_mode()
3289 	qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);  in qcom_qmp_phy_enable_autonomous_mode()
3291 	qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],  in qcom_qmp_phy_enable_autonomous_mode()
3295 	qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);  in qcom_qmp_phy_enable_autonomous_mode()
3305 	void __iomem *pcs = qphy->pcs;  in qcom_qmp_phy_disable_autonomous_mode()  local
3312 	qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],  in qcom_qmp_phy_disable_autonomous_mode()
3315 	qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);  in qcom_qmp_phy_disable_autonomous_mode()
3317 	qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);  in qcom_qmp_phy_disable_autonomous_mode()
3744 	 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.  in qcom_qmp_phy_create()
3756 	qphy->pcs = of_iomap(np, 2);  in qcom_qmp_phy_create()
3757 	if (!qphy->pcs)  in qcom_qmp_phy_create()