Lines Matching refs:RXTX_REG127
450 #define RXTX_REG127 0x0fe macro
1102 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_sata_cfg_lanes()
1104 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_sata_cfg_lanes()
1370 serdes_setbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1377 serdes_clrbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1386 serdes_setbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1393 serdes_clrbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1510 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1515 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1563 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1566 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()