30 #define HDMI_CON2	0x08  macro
75 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);  in mtk_hdmi_pll_prepare()
78 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);  in mtk_hdmi_pll_prepare()
81 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);  in mtk_hdmi_pll_prepare()
96 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);  in mtk_hdmi_pll_unprepare()
99 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);  in mtk_hdmi_pll_unprepare()
102 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);  in mtk_hdmi_pll_unprepare()
130 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);  in mtk_hdmi_pll_set_rate()
135 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),  in mtk_hdmi_pll_set_rate()
185 	val = (readl(hdmi_phy->regs + HDMI_CON2)  in mtk_hdmi_pll_recalc_rate()
189 	if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV)  in mtk_hdmi_pll_recalc_rate()
208 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);  in mtk_hdmi_phy_enable_tmds()
211 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);  in mtk_hdmi_phy_enable_tmds()
214 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);  in mtk_hdmi_phy_enable_tmds()
226 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);  in mtk_hdmi_phy_disable_tmds()
229 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);  in mtk_hdmi_phy_disable_tmds()
232 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);  in mtk_hdmi_phy_disable_tmds()