Lines Matching +full:pch +full:- +full:msi +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
63 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
64 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
65 (f->vendor == dev->vendor || in pci_do_fixups()
66 f->vendor == (u16) PCI_ANY_ID) && in pci_do_fixups()
67 (f->device == dev->device || in pci_do_fixups()
68 f->device == (u16) PCI_ANY_ID)) { in pci_do_fixups()
71 hook = offset_to_ptr(&f->hook_offset); in pci_do_fixups()
73 hook = f->hook; in pci_do_fixups()
199 * key system devices. For devices that need to have mmio decoding always-on,
200 * we need to set the dev->mmio_always_on bit.
204 dev->mmio_always_on = 1; in quirk_mmio_always_on()
216 dev->broken_parity_status = 1; /* This device gives false positives */ in quirk_mellanox_tavor()
236 if (!(dlc & 1<<1)) { in quirk_passive_release()
238 dlc |= 1<<1; in quirk_passive_release()
249 * contacts at VIA ask them for me please -- Alan
257 isa_dma_bridge_buggy = 1; in quirk_isa_dma_hangs()
293 /* Chipsets where PCI->PCI transfers vanish or hang */
331 * Made according to a Windows driver-based patch by George E. Breese;
333 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
352 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; in quirk_vialatency()
356 if (p->revision < 0x40 || p->revision > 0x42) in quirk_vialatency()
364 if (p->revision < 0x10 || p->revision > 0x12) in quirk_vialatency()
386 busarb &= ~(1<<5); in quirk_vialatency()
387 busarb |= (1<<4); in quirk_vialatency()
456 dev->cfg_size = 0xA0; in quirk_citrine()
466 dev->cfg_size = 0x600; in quirk_nfp6000()
479 struct resource *r = &dev->resource[i]; in quirk_extend_bar_to_page()
481 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { in quirk_extend_bar_to_page()
482 r->end = PAGE_SIZE - 1; in quirk_extend_bar_to_page()
483 r->start = 0; in quirk_extend_bar_to_page()
484 r->flags |= IORESOURCE_UNSET; in quirk_extend_bar_to_page()
494 * If it's needed, re-allocate the region.
498 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
500 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { in quirk_s3_64M()
501 r->flags |= IORESOURCE_UNSET; in quirk_s3_64M()
502 r->start = 0; in quirk_s3_64M()
503 r->end = 0x3ffffff; in quirk_s3_64M()
514 struct resource *res = dev->resource + pos; in quirk_io()
521 res->name = pci_name(dev); in quirk_io()
522 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; in quirk_io()
523 res->flags |= in quirk_io()
525 region &= ~(size - 1); in quirk_io()
529 bus_region.end = region + size - 1; in quirk_io()
530 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io()
542 * CS553x's ISA PCI BARs may also be read-only (ref:
543 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
551 quirk_io(dev, 1, 256, name); /* GPIO */ in quirk_cs5536_vsa()
564 struct resource *res = dev->resource + nr; in quirk_io_region()
567 region &= ~(size - 1); in quirk_io_region()
572 res->name = pci_name(dev); in quirk_io_region()
573 res->flags = IORESOURCE_IO; in quirk_io_region()
577 bus_region.end = region + size - 1; in quirk_io_region()
578 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io_region()
586 * between 0x3b0->0x3bb or read 0x3d3
610 u32 class = pdev->class; in quirk_amd_nl_class()
613 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_amd_nl_class()
614 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_amd_nl_class()
615 class, pdev->class); in quirk_amd_nl_class()
623 * devices should use dwc3-haps driver. Change these devices' class code to
624 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
629 u32 class = pdev->class; in quirk_synopsys_haps()
631 switch (pdev->device) { in quirk_synopsys_haps()
635 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_synopsys_haps()
636 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_synopsys_haps()
637 class, pdev->class); in quirk_synopsys_haps()
658 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); in quirk_ali7101_acpi()
674 unsigned bit = size >> 1; in piix4_io_quirk()
684 base &= -size; in piix4_io_quirk()
685 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); in piix4_io_quirk()
700 unsigned bit = size >> 1; in piix4_mem_quirk()
710 base &= -size; in piix4_mem_quirk()
711 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); in piix4_mem_quirk()
725 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); in quirk_piix4_acpi()
736 if (res_a & (1 << 29)) { in quirk_piix4_acpi()
737 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); in quirk_piix4_acpi()
738 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); in quirk_piix4_acpi()
741 if (res_a & (1 << 30)) { in quirk_piix4_acpi()
742 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); in quirk_piix4_acpi()
743 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); in quirk_piix4_acpi()
745 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); in quirk_piix4_acpi()
746 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); in quirk_piix4_acpi()
763 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
785 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, in quirk_ich4_lpc_acpi()
810 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, in ich6_lpc_acpi_gpio()
823 if (!(val & 1)) in ich6_lpc_generic_decode()
837 base &= ~(size-1); in ich6_lpc_generic_decode()
843 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); in ich6_lpc_generic_decode()
851 /* ICH6-specific generic IO decode */ in quirk_ich6_lpc()
852 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); in quirk_ich6_lpc()
853 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); in quirk_ich6_lpc()
867 if (!(val & 1)) in ich7_lpc_generic_decode()
870 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ in ich7_lpc_generic_decode()
882 /* ICH7-10 has the same common LPC generic IO decode registers */
889 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); in quirk_ich7_lpc()
914 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
930 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, in quirk_vt82c686_acpi()
931 "vt82c686 HW-mon"); in quirk_vt82c686_acpi()
945 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); in quirk_vt8235_acpi()
950 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
951 * back-to-back: Disable fast back-to-back on the secondary bus segment
958 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); in quirk_xio2000a()
959 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { in quirk_xio2000a()
973 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
976 * TODO: When we have device-specific interrupt routers, this code will go
983 if (nr_ioapics < 1) in quirk_via_ioapic()
986 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ in quirk_via_ioapic()
998 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1010 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); in quirk_via_vt8237_bypass_apic_deassert()
1018 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1028 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1040 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ in quirk_cavium_sriov_rnm_link()
1041 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1042 dev->sriov->link = dev->devfn; in quirk_cavium_sriov_rnm_link()
1049 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1053 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1054 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", in quirk_amd_8131_mmrbc()
1055 dev->revision); in quirk_amd_8131_mmrbc()
1056 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; in quirk_amd_8131_mmrbc()
1066 * -jgarzik
1076 d->irq = irq; in quirk_via_acpi()
1082 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1087 switch (dev->device) { in quirk_via_bridge()
1094 via_vlink_dev_lo = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1095 via_vlink_dev_hi = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1122 * quirk_via_vlink - VIA VLink IRQ number update
1137 if (via_vlink_dev_lo == -1) in quirk_via_vlink()
1140 new_irq = dev->irq; in quirk_via_vlink()
1147 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1148 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) in quirk_via_vlink()
1173 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); in quirk_vt82c598_id()
1208 pcic |= (1 << 23); /* Required in this mode */ in quirk_amd_ordering()
1216 * DreamWorks-provided workaround for Dunord I-3000 problem
1224 struct resource *r = &dev->resource[1]; in quirk_dunord()
1226 r->flags |= IORESOURCE_UNSET; in quirk_dunord()
1227 r->start = 0; in quirk_dunord()
1228 r->end = 0xffffff; in quirk_dunord()
1233 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1235 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1239 dev->transparent = 1; in quirk_transparent_bridge()
1274 if (pdev->revision != 0x04) /* Only C0 requires this */ in quirk_disable_pxb()
1277 if (config & (1<<6)) { in quirk_disable_pxb()
1278 config &= ~(1<<6); in quirk_disable_pxb()
1288 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ in quirk_amd_ide_mode()
1294 pci_write_config_byte(pdev, 0x40, tmp|1); in quirk_amd_ide_mode()
1295 pci_write_config_byte(pdev, 0x9, 1); in quirk_amd_ide_mode()
1299 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; in quirk_amd_ide_mode()
1319 pdev->class &= ~5; in quirk_svwks_csb5ide()
1326 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1333 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { in quirk_ide_samemode()
1336 pdev->class &= ~5; in quirk_ide_samemode()
1345 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; in quirk_no_ata_d3()
1361 * This was originally an Alpha-specific thing, but it really fits here.
1362 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1366 dev->class = PCI_CLASS_BRIDGE_EISA << 8; in quirk_eisa_bridge()
1379 * becomes necessary to do this tweak in two steps -- the chosen trigger
1380 * is either the Host bridge (preferred) or on-board VGA controller.
1393 * the DSDT and double-check that there is no code accessing the SMBus.
1399 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_smbus_hostbridge()
1400 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) in asus_hides_smbus_hostbridge()
1401 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1402 case 0x8025: /* P4B-LX */ in asus_hides_smbus_hostbridge()
1406 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1408 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) in asus_hides_smbus_hostbridge()
1409 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1410 case 0x80b1: /* P4GE-V */ in asus_hides_smbus_hostbridge()
1412 case 0x8093: /* P4B533-V */ in asus_hides_smbus_hostbridge()
1413 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1415 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) in asus_hides_smbus_hostbridge()
1416 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1418 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1420 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) in asus_hides_smbus_hostbridge()
1421 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1423 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1425 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) in asus_hides_smbus_hostbridge()
1426 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1427 case 0x80c9: /* PU-DLS */ in asus_hides_smbus_hostbridge()
1428 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1430 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) in asus_hides_smbus_hostbridge()
1431 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1435 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1437 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1438 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1441 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1443 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1444 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1445 case 0x80f2: /* P4P800-X */ in asus_hides_smbus_hostbridge()
1446 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1448 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) in asus_hides_smbus_hostbridge()
1449 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1452 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1454 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { in asus_hides_smbus_hostbridge()
1455 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1456 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1459 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1461 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1462 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1466 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1468 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) in asus_hides_smbus_hostbridge()
1469 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1471 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1473 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { in asus_hides_smbus_hostbridge()
1474 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1475 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1477 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1479 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { in asus_hides_smbus_hostbridge()
1480 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1481 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1483 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1485 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) in asus_hides_smbus_hostbridge()
1486 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1487 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ in asus_hides_smbus_hostbridge()
1490 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1491 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1493 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) in asus_hides_smbus_hostbridge()
1494 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1499 * subvendor/subdevice IDs and on-board VGA in asus_hides_smbus_hostbridge()
1502 * Controller #1 */ in asus_hides_smbus_hostbridge()
1503 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1505 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) in asus_hides_smbus_hostbridge()
1506 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1510 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1511 asus_hides_smbus = 1; in asus_hides_smbus_hostbridge()
1650 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); in quirk_sis_503()
1662 dev->device = devid; in quirk_sis_503()
1672 * -- bjd
1679 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_ac97_lpc()
1680 if (dev->device == PCI_DEVICE_ID_VIA_8237) in asus_hides_ac97_lpc()
1681 asus_hides_ac97 = 1; in asus_hides_ac97_lpc()
1713 if (PCI_FUNC(pdev->devfn)) in quirk_jmicron_ata()
1719 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ in quirk_jmicron_ata()
1720 conf5 &= ~(1 << 24); /* Clear bit 24 */ in quirk_jmicron_ata()
1722 switch (pdev->device) { in quirk_jmicron_ata()
1733 conf5 |= (1 << 24); in quirk_jmicron_ata()
1740 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ in quirk_jmicron_ata()
1754 pdev->hdr_type = hdr & 0x7f; in quirk_jmicron_ata()
1755 pdev->multifunction = !!(hdr & 0x80); in quirk_jmicron_ata()
1758 pdev->class = class >> 8; in quirk_jmicron_ata()
1783 if (dev->multifunction) { in quirk_jmicron_async_suspend()
1784 device_disable_async_suspend(&dev->dev); in quirk_jmicron_async_suspend()
1785 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); in quirk_jmicron_async_suspend()
1798 if ((pdev->class >> 8) != 0xff00) in quirk_alder_ioapic()
1802 * The first BAR is the location of the IO-APIC... we must in quirk_alder_ioapic()
1807 insert_resource(&iomem_resource, &pdev->resource[0]); in quirk_alder_ioapic()
1813 for (i = 1; i < PCI_STD_NUM_BARS; i++) in quirk_alder_ioapic()
1814 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); in quirk_alder_ioapic()
1821 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); in quirk_no_msi()
1822 dev->no_msi = 1; in quirk_no_msi()
1833 pdev->no_msi = 1; in quirk_pcie_mch()
1842 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1843 * together on certain PXH-based systems.
1847 dev->no_msi = 1; in quirk_pcie_pxh()
1848 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); in quirk_pcie_pxh()
1863 dev->no_d1d2 = 1; in quirk_intel_pcie_pm()
1889 if (dev->d3hot_delay >= delay) in quirk_d3hot_delay()
1892 dev->d3hot_delay = delay; in quirk_d3hot_delay()
1893 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", in quirk_d3hot_delay()
1894 dev->d3hot_delay); in quirk_d3hot_delay()
1899 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && in quirk_radeon_pm()
1900 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
1911 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1925 noioapicreroute = 1; in dmi_disable_ioapicreroute()
1926 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); in dmi_disable_ioapicreroute()
1937 .ident = "ASUSTek Computer INC. M2N-LR",
1940 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1958 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; in quirk_reroute_to_boot_interrupts_intel()
1960 dev->vendor, dev->device); in quirk_reroute_to_boot_interrupts_intel()
1985 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1986 * 300641-004US, section 5.7.3.
1988 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
1989 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
1990 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
1991 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
1992 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
1993 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
1994 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
1995 * Core IO on Xeon D-1500, see Intel order no 332051-001.
1999 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
2002 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
2012 switch (dev->device) { in quirk_disable_intel_boot_interrupt()
2023 case 0x6f28: /* Xeon D-1500 */ in quirk_disable_intel_boot_interrupt()
2035 dev->vendor, dev->device); in quirk_disable_intel_boot_interrupt()
2038 * Device 29 Func 5 Device IDs of IO-APIC
2074 /* Disable boot interrupts on HT-1000 */
2076 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2100 dev->vendor, dev->device); in quirk_disable_broadcom_boot_interrupt()
2109 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2113 #define AMD_813X_NOIOAMODE (1<<0)
2123 if ((dev->revision == AMD_813X_REV_B1) || in quirk_disable_amd_813x_boot_interrupt()
2124 (dev->revision == AMD_813X_REV_B2)) in quirk_disable_amd_813x_boot_interrupt()
2132 dev->vendor, dev->device); in quirk_disable_amd_813x_boot_interrupt()
2151 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2156 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2163 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2165 * Re-allocate the region if needed...
2169 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2171 if (r->start & 0x8) { in quirk_tc86c001_ide()
2172 r->flags |= IORESOURCE_UNSET; in quirk_tc86c001_ide()
2173 r->start = 0; in quirk_tc86c001_ide()
2174 r->end = 0xf; in quirk_tc86c001_ide()
2186 * Re-allocate the regions to a 256-byte boundary if necessary.
2193 if (dev->revision >= 2) in quirk_plx_pci9050()
2195 for (bar = 0; bar <= 1; bar++) in quirk_plx_pci9050()
2198 struct resource *r = &dev->resource[bar]; in quirk_plx_pci9050()
2199 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", in quirk_plx_pci9050()
2201 r->flags |= IORESOURCE_UNSET; in quirk_plx_pci9050()
2202 r->start = 0; in quirk_plx_pci9050()
2203 r->end = 0xff; in quirk_plx_pci9050()
2222 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2223 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2235 switch (dev->device) { in quirk_netmos()
2238 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in quirk_netmos()
2239 dev->subsystem_device == 0x0299) in quirk_netmos()
2248 dev->device, num_parallel, num_serial); in quirk_netmos()
2249 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | in quirk_netmos()
2250 (dev->class & 0xff); in quirk_netmos()
2263 switch (dev->device) { in quirk_e100_interrupt()
2288 * re-enable them when it's ready. in quirk_e100_interrupt()
2299 if (dev->pm_cap) { in quirk_e100_interrupt()
2300 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in quirk_e100_interrupt()
2315 writeb(1, csr + 3); in quirk_e100_interrupt()
2354 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2368 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2377 dev->clear_retrain_link = 1; in quirk_enable_clear_retrain_link()
2386 u32 class = dev->class; in fixup_rev1_53c810()
2389 * rev 1 ncr53c810 chips don't set the class at all which means in fixup_rev1_53c810()
2395 dev->class = PCI_CLASS_STORAGE_SCSI << 8; in fixup_rev1_53c810()
2396 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", in fixup_rev1_53c810()
2397 class, dev->class); in fixup_rev1_53c810()
2401 /* Enable 1k I/O space granularity on the Intel P64H2 */
2409 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); in quirk_p64h2_1k_io()
2410 dev->io_window_1k = 1; in quirk_p64h2_1k_io()
2444 * VT6212L is found -- the CX700 core itself also contains a USB in quirk_via_cx700_pci_parking_caching()
2454 * p should contain the first (internal) VT6212L -- see if we have in quirk_via_cx700_pci_parking_caching()
2476 /* Set PCI Master Bus time-out to "1x16 PCLK" */ in quirk_via_cx700_pci_parking_caching()
2508 * DRBs - this is where we expose device 6.
2509 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2527 * Some chipsets do not support MSI. We cannot easily rely on setting
2531 * MSI globally.
2536 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); in quirk_disable_all_msi()
2547 /* Disable MSI on chipsets that are known to not support it */
2550 if (dev->subordinate) { in quirk_disable_msi()
2551 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); in quirk_disable_msi()
2552 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_disable_msi()
2569 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); in quirk_amd_780_apc_msi()
2571 if (apc_bridge->device == 0x9602) in quirk_amd_780_apc_msi()
2580 * Go through the list of HyperTransport capabilities and return 1 if a HT
2581 * MSI capability is found and enabled.
2588 while (pos && ttl--) { in msi_ht_cap_enabled()
2593 pci_info(dev, "Found %s HT MSI Mapping\n", in msi_ht_cap_enabled()
2605 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2608 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { in quirk_msi_ht_cap()
2609 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); in quirk_msi_ht_cap()
2610 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_msi_ht_cap()
2617 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2618 * if the MSI capability is set in any of these mappings.
2624 if (!dev->subordinate) in quirk_nvidia_ck804_msi_ht_cap()
2628 * Check HT MSI cap on this chipset and the root one. A single one in quirk_nvidia_ck804_msi_ht_cap()
2629 * having MSI is enough to be sure that MSI is supported. in quirk_nvidia_ck804_msi_ht_cap()
2631 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2635 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); in quirk_nvidia_ck804_msi_ht_cap()
2636 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_nvidia_ck804_msi_ht_cap()
2643 /* Force enable MSI mapping capability on HT bridges */
2649 while (pos && ttl--) { in ht_enable_msi_mapping()
2654 pci_info(dev, "Enabling HT MSI Mapping\n"); in ht_enable_msi_mapping()
2670 * The P5N32-SLI motherboards from Asus have a problem with MSI
2671 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2672 * also affects other devices. As for now, turn off MSI for this device.
2679 (strstr(board_name, "P5N32-SLI PREMIUM") || in nvenet_msi_disable()
2680 strstr(board_name, "P5N32-E SLI"))) { in nvenet_msi_disable()
2681 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); in nvenet_msi_disable()
2682 dev->no_msi = 1; in nvenet_msi_disable()
2690 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2692 * generate MSI interrupts for PME and AER events instead only INTx interrupts
2693 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2695 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2700 dev->no_msi = 1; in pci_quirk_nvidia_tegra_disable_rp_msi()
2761 if (cfg & ((1 << 2) | (1 << 15))) { in nvbridge_check_legacy_irq_routing()
2763 cfg &= ~((1 << 2) | (1 << 15)); in nvbridge_check_legacy_irq_routing()
2779 /* Check if there is HT MSI cap or enabled on this device */ in ht_check_msi_mapping()
2781 while (pos && ttl--) { in ht_check_msi_mapping()
2784 if (found < 1) in ht_check_msi_mapping()
2785 found = 1; in ht_check_msi_mapping()
2809 dev_no = host_bridge->devfn >> 3; in host_bridge_with_leaf()
2810 for (i = dev_no + 1; i < 0x20; i++) { in host_bridge_with_leaf()
2811 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2823 found = 1; in host_bridge_with_leaf()
2849 ctrl_off = ((flags >> 10) & 1) ? in is_end_of_ht_chain()
2853 if (ctrl & (1 << 6)) in is_end_of_ht_chain()
2854 end = 1; in is_end_of_ht_chain()
2867 dev_no = dev->devfn >> 3; in nv_ht_enable_msi_mapping()
2868 for (i = dev_no; i >= 0; i--) { in nv_ht_enable_msi_mapping()
2869 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
2875 found = 1; in nv_ht_enable_msi_mapping()
2904 while (pos && ttl--) { in ht_disable_msi_mapping()
2909 pci_info(dev, "Disabling HT MSI Mapping\n"); in ht_disable_msi_mapping()
2928 /* check if there is HT MSI cap or enabled on this device */ in __nv_msi_ht_cap_quirk()
2931 /* no HT MSI CAP */ in __nv_msi_ht_cap_quirk()
2936 * HT MSI mapping should be disabled on devices that are below in __nv_msi_ht_cap_quirk()
2937 * a non-Hypertransport host bridge. Locate the host bridge... in __nv_msi_ht_cap_quirk()
2939 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
2949 if (found == 1) { in __nv_msi_ht_cap_quirk()
2959 /* HT MSI is not enabled */ in __nv_msi_ht_cap_quirk()
2960 if (found == 1) in __nv_msi_ht_cap_quirk()
2963 /* Host bridge is not to HT, disable HT MSI mapping on this device */ in __nv_msi_ht_cap_quirk()
2972 return __nv_msi_ht_cap_quirk(dev, 1); in nv_msi_ht_cap_quirk_all()
2986 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_bug()
2994 * SB700 MSI issue will be fixed at HW level from revision A21; in quirk_msi_intx_disable_ati_bug()
3003 if ((p->revision < 0x3B) && (p->revision >= 0x30)) in quirk_msi_intx_disable_ati_bug()
3004 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_ati_bug()
3010 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ in quirk_msi_intx_disable_qca_bug()
3011 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3013 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_qca_bug()
3077 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3080 * Notice that this quirk also disables MSI (which may work, but hasn't been
3081 * tested), since currently there is no standard way to disable only MSI-X.
3088 dev->no_msi = 1; in quirk_al_msi_disable()
3089 pci_warn(dev, "Disabling MSI/MSI-X\n"); in quirk_al_msi_disable()
3097 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3104 dev->is_hotplug_bridge = 1; in quirk_hotplug_bridge()
3121 * MMC controller - so the SDHCI driver never sees them.
3131 * #1, and this will confuse the PCI core.
3145 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_rl5c476()
3176 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_r5c832()
3183 * 0x150 - SD2.0 mode enable for changing base clock in ricoh_mmc_fixup_r5c832()
3185 * 0xe1 - Base clock frequency in ricoh_mmc_fixup_r5c832()
3186 * 0x32 - 50Mhz new clock frequency in ricoh_mmc_fixup_r5c832()
3187 * 0xf9 - Key register for 0x150 in ricoh_mmc_fixup_r5c832()
3188 * 0xfc - key register for 0xe1 in ricoh_mmc_fixup_r5c832()
3190 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || in ricoh_mmc_fixup_r5c832()
3191 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { in ricoh_mmc_fixup_r5c832()
3226 #define VTD_MSK_SPEC_ERRORS (1 << 31)
3228 * This is a quirk for masking VT-d spec-defined errors to platform error
3231 * on the RAS config settings of the platform) when a VT-d fault happens.
3234 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3250 u32 class = dev->class; in fixup_ti816x_class()
3253 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; in fixup_ti816x_class()
3254 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", in fixup_ti816x_class()
3255 class, dev->class); in fixup_ti816x_class()
3266 dev->pcie_mpss = 1; /* 256 bytes */ in fixup_mpss_256()
3281 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3304 if (!(rcc & (1 << 10))) in quirk_intel_mc_errata()
3307 rcc &= ~(1 << 10); in quirk_intel_mc_errata()
3317 /* Intel 5000 series memory controllers and ports 2-7 */
3332 /* Intel 5100 series memory controllers and ports 2-7 */
3359 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3365 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3374 * and the interrupt ends up -somewhere-.
3414 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3420 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3450 dev->broken_intx_masking = 1; in quirk_broken_intx_masking()
3463 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3470 * DisINTx can be set but the interrupt status bit is non-functional.
3510 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3526 if (pdev->device == mellanox_broken_intx_devs[i]) { in mellanox_check_broken_intx_masking()
3527 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3533 * Getting here means Connect-IB cards and up. Connect-IB has no INTx in mellanox_check_broken_intx_masking()
3536 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) in mellanox_check_broken_intx_masking()
3539 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && in mellanox_check_broken_intx_masking()
3540 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) in mellanox_check_broken_intx_masking()
3543 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ in mellanox_check_broken_intx_masking()
3551 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); in mellanox_check_broken_intx_masking()
3557 fw_sub_min = ioread32be(fw_ver + 1); in mellanox_check_broken_intx_masking()
3563 …pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW… in mellanox_check_broken_intx_masking()
3564 fw_major, fw_minor, fw_subminor, pdev->device == in mellanox_check_broken_intx_masking()
3566 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3579 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; in quirk_no_bus_reset()
3588 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3596 * The device will throw a Link Down error on AER-capable systems and
3631 if (!pci_is_root_bus(dev->bus)) in quirk_no_pm_reset()
3632 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; in quirk_no_pm_reset()
3636 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3637 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3647 * Thunderbolt controllers with broken MSI hotplug signaling:
3648 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3649 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3653 if (pdev->is_hotplug_bridge && in quirk_thunderbolt_hotplug_msi()
3654 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || in quirk_thunderbolt_hotplug_msi()
3655 pdev->revision <= 1)) in quirk_thunderbolt_hotplug_msi()
3656 pdev->no_msi = 1; in quirk_thunderbolt_hotplug_msi()
3703 bridge = ACPI_HANDLE(&dev->dev); in quirk_apple_poweroff_thunderbolt()
3721 acpi_execute_simple_method(SXIO, NULL, 1); in quirk_apple_poweroff_thunderbolt()
3734 * Following are device-specific reset methods which can be used to
3735 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3741 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf in reset_intel_82599_sfp_virtfn()
3771 return -ENOMEM; in reset_ivb_igd()
3802 /* Device-specific reset method for Chelsio T4-based adapters */
3809 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating in reset_chelsio_generic_dev()
3810 * that we have no device-specific reset method. in reset_chelsio_generic_dev()
3812 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3813 return -ENOTTY; in reset_chelsio_generic_dev()
3839 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts in reset_chelsio_generic_dev()
3840 * are disabled when an MSI-X interrupt message needs to be delivered. in reset_chelsio_generic_dev()
3841 * So we briefly re-enable MSI-X interrupts for the duration of the in reset_chelsio_generic_dev()
3843 * MSI-X state. in reset_chelsio_generic_dev()
3845 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); in reset_chelsio_generic_dev()
3847 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, in reset_chelsio_generic_dev()
3870 * FLR where config space reads from the device return -1. We seem to be
3887 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || in nvme_disable_and_flr()
3889 return -ENOTTY; in nvme_disable_and_flr()
3896 return -ENOTTY; in nvme_disable_and_flr()
3924 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; in nvme_disable_and_flr()
3958 return -ENOTTY; in delay_250ms_after_flr()
3972 #define HINIC_VF_FLR_CAP_BIT (1UL << 30)
3974 #define HINIC_VF_FLR_PROC_BIT (1UL << 18)
3977 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
3989 return -ENOTTY; in reset_hinic_vf_dev()
3995 return -ENOTTY; in reset_hinic_vf_dev()
4050 * These device-specific reset methods are here rather than in a driver
4058 for (i = pci_dev_reset_methods; i->reset; i++) { in pci_dev_specific_reset()
4059 if ((i->vendor == dev->vendor || in pci_dev_specific_reset()
4060 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_reset()
4061 (i->device == dev->device || in pci_dev_specific_reset()
4062 i->device == (u16)PCI_ANY_ID)) in pci_dev_specific_reset()
4063 return i->reset(dev, probe); in pci_dev_specific_reset()
4066 return -ENOTTY; in pci_dev_specific_reset()
4071 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4072 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4085 if (PCI_FUNC(dev->devfn) != 1) in quirk_dma_func1_alias()
4086 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); in quirk_dma_func1_alias()
4090 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
4091 * SKUs function 1 is present and is a legacy IDE controller, in other
4142 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4152 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4164 .driver_data = PCI_DEVFN(1, 0) },
4167 .driver_data = PCI_DEVFN(1, 0) },
4177 pci_add_dma_alias(dev, id->driver_data, 1); in quirk_fixed_dma_alias()
4182 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4187 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4188 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4192 if (!pci_is_root_bus(pdev->bus) && in quirk_use_pcie_bridge_dma_alias()
4193 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && in quirk_use_pcie_bridge_dma_alias()
4194 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && in quirk_use_pcie_bridge_dma_alias()
4195 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) in quirk_use_pcie_bridge_dma_alias()
4196 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; in quirk_use_pcie_bridge_dma_alias()
4213 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4218 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); in quirk_mic_x200_dma_alias()
4219 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); in quirk_mic_x200_dma_alias()
4220 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); in quirk_mic_x200_dma_alias()
4226 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4261 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; in quirk_bridge_cavm_thrx2_pcie_root()
4269 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4274 u32 class = pdev->class; in quirk_tw686x_class()
4277 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; in quirk_tw686x_class()
4278 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", in quirk_tw686x_class()
4279 class, pdev->class); in quirk_tw686x_class()
4297 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; in quirk_relaxedordering_disable()
4368 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4384 * If a non-compliant device generates a completion with a different
4386 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4390 * If the non-compliant device generates completions with zero attributes
4412 dev_name(&pdev->dev)); in quirk_disable_root_port_attributes()
4430 if ((pdev->device & 0xff00) == 0x5400) in quirk_chelsio_T5_disable_root_port_attributes()
4437 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4443 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4450 return 1; in pci_acs_ctrl_enabled()
4455 * AMD has indicated that the devices below do not support peer-to-peer
4458 * peer-to-peer between functions can claim to support a subset of ACS.
4486 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) in pci_quirk_amd_sb_acs()
4487 return -ENODEV; in pci_quirk_amd_sb_acs()
4492 return -ENODEV; in pci_quirk_amd_sb_acs()
4501 return -ENODEV; in pci_quirk_amd_sb_acs()
4510 switch (dev->device) { in pci_quirk_cavium_acs_match()
4527 return -ENOTTY; in pci_quirk_cavium_acs()
4544 * X-Gene Root Ports matching this quirk do not allow peer-to-peer in pci_quirk_xgene_acs()
4554 * But the implementation could block peer-to-peer transactions between them
4555 * and provide ACS-like functionality.
4562 return -ENOTTY; in pci_quirk_zhaoxin_pcie_ports_acs()
4564 switch (dev->device) { in pci_quirk_zhaoxin_pcie_ports_acs()
4576 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4582 /* Ibexpeak PCH */
4585 /* Cougarpoint PCH */
4588 /* Pantherpoint PCH */
4591 /* Lynxpoint-H PCH */
4594 /* Lynxpoint-LP PCH */
4597 /* Wildcat PCH */
4600 /* Patsburg (X79) PCH */
4602 /* Wellsburg (X99) PCH */
4605 /* Lynx Point (9 series) PCH */
4613 /* Filter out a few obvious non-matches first */ in pci_quirk_intel_pch_acs_match()
4618 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) in pci_quirk_intel_pch_acs_match()
4627 return -ENOTTY; in pci_quirk_intel_pch_acs()
4629 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) in pci_quirk_intel_pch_acs()
4637 * These QCOM Root Ports do provide ACS-like features to disable peer
4641 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4667 return -ENOTTY; in pci_quirk_al_acs()
4671 * but do include ACS-like functionality. The hardware doesn't support in pci_quirk_al_acs()
4672 * peer-to-peer transactions via the root port and each has a unique in pci_quirk_al_acs()
4679 return acs_flags ? 0 : 1; in pci_quirk_al_acs()
4683 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4684 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4685 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4690 * found in volume 1 of the datasheet[2]:
4692 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4693 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4701 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4705 * 0xa290-0xa29f PCI Express Root port #{0-16}
4706 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4712 * August 2017, Revision 002, Document#: 334660-002)[6]
4715 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4717 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4719 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4720 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4721 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4722 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4723 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4724 …ww.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-…
4725 …tel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datas…
4732 switch (dev->device) { in pci_quirk_intel_spt_pch_acs_match()
4750 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4752 pos = dev->acs_cap; in pci_quirk_intel_spt_pch_acs()
4754 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4771 * in their ACS capability if they support peer-to-peer transactions. in pci_quirk_mf_endpoint_acs()
4773 * perform peer-to-peer with other functions, allowing us to mask out in pci_quirk_mf_endpoint_acs()
4785 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, in pci_quirk_rciep_acs()
4786 * "Root-Complex Peer to Peer Considerations". in pci_quirk_rciep_acs()
4789 return -ENOTTY; in pci_quirk_rciep_acs()
4799 * they do not allow peer-to-peer transactions between Root Ports. in pci_quirk_brcm_acs()
4869 /* 82571 (Quads omitted due to non-ACS switch) */
4883 /* Intel PCH root ports */
4886 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4887 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4890 /* Cavium multi-function devices */
4894 /* APM X-Gene */
4905 /* Broadcom multi-function device */
4913 /* Zhaoxin multi-function devices */
4918 /* LX2xx0A : without security features + CAN-FD */
4922 /* LX2xx0C : security features + CAN-FD */
4934 /* LX2xx2A : without security features + CAN-FD */
4938 /* LX2xx2C : security features + CAN-FD */
4956 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4961 * -ENOTTY: No quirk applies to this device; we can't tell whether the
4973 * or control to indicate their support here. Multi-function express in pci_dev_specific_acs_enabled()
4974 * devices which do not allow internal peer-to-peer between functions, in pci_dev_specific_acs_enabled()
4977 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { in pci_dev_specific_acs_enabled()
4978 if ((i->vendor == dev->vendor || in pci_dev_specific_acs_enabled()
4979 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_acs_enabled()
4980 (i->device == dev->device || in pci_dev_specific_acs_enabled()
4981 i->device == (u16)PCI_ANY_ID)) { in pci_dev_specific_acs_enabled()
4982 ret = i->acs_enabled(dev, acs_flags); in pci_dev_specific_acs_enabled()
4988 return -ENOTTY; in pci_dev_specific_acs_enabled()
4996 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
5000 /* Backbone Peer Non-Posted Disable */
5001 #define INTEL_BSPR_REG_BPNPD (1 << 8)
5003 #define INTEL_BSPR_REG_BPPD (1 << 9)
5016 * Read the RCBA register from the LPC (D31:F0). PCH root ports in pci_quirk_enable_intel_lpc_acs()
5020 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5023 return -EINVAL; in pci_quirk_enable_intel_lpc_acs()
5028 return -ENOMEM; in pci_quirk_enable_intel_lpc_acs()
5032 * therefore read-only. If both posted and non-posted peer cycles are in pci_quirk_enable_intel_lpc_acs()
5055 #define INTEL_MPC_REG_IRBNCE (1 << 26)
5080 * if dev->external_facing || dev->untrusted
5085 return -ENOTTY; in pci_quirk_enable_intel_pch_acs()
5088 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); in pci_quirk_enable_intel_pch_acs()
5094 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; in pci_quirk_enable_intel_pch_acs()
5096 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); in pci_quirk_enable_intel_pch_acs()
5107 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5109 pos = dev->acs_cap; in pci_quirk_enable_intel_spt_pch_acs()
5111 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5121 if (dev->external_facing || dev->untrusted) in pci_quirk_enable_intel_spt_pch_acs()
5126 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); in pci_quirk_enable_intel_spt_pch_acs()
5137 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5139 pos = dev->acs_cap; in pci_quirk_disable_intel_spt_pch_acs_redir()
5141 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5150 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); in pci_quirk_disable_intel_spt_pch_acs_redir()
5177 if ((p->vendor == dev->vendor || in pci_dev_specific_enable_acs()
5178 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5179 (p->device == dev->device || in pci_dev_specific_enable_acs()
5180 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5181 p->enable_acs) { in pci_dev_specific_enable_acs()
5182 ret = p->enable_acs(dev); in pci_dev_specific_enable_acs()
5188 return -ENOTTY; in pci_dev_specific_enable_acs()
5198 if ((p->vendor == dev->vendor || in pci_dev_specific_disable_acs_redir()
5199 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5200 (p->device == dev->device || in pci_dev_specific_disable_acs_redir()
5201 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5202 p->disable_acs_redir) { in pci_dev_specific_disable_acs_redir()
5203 ret = p->disable_acs_redir(dev); in pci_dev_specific_disable_acs_redir()
5209 return -ENOTTY; in pci_dev_specific_disable_acs_redir()
5215 * Next Capability pointer in the MSI Capability Structure should point to
5227 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) in quirk_intel_qat_vf_cap()
5230 /* Bail if MSI Capability Structure is not found for some reason */ in quirk_intel_qat_vf_cap()
5236 * Bail if Next Capability pointer in the MSI Capability Structure in quirk_intel_qat_vf_cap()
5239 pci_read_config_byte(pdev, pos + 1, &next_cap); in quirk_intel_qat_vf_cap()
5247 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() in quirk_intel_qat_vf_cap()
5260 pdev->pcie_cap = pos; in quirk_intel_qat_vf_cap()
5262 pdev->pcie_flags_reg = reg16; in quirk_intel_qat_vf_cap()
5264 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; in quirk_intel_qat_vf_cap()
5266 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; in quirk_intel_qat_vf_cap()
5269 pdev->cfg_size = PCI_CFG_SPACE_SIZE; in quirk_intel_qat_vf_cap()
5279 state->cap.cap_nr = PCI_CAP_ID_EXP; in quirk_intel_qat_vf_cap()
5280 state->cap.cap_extended = 0; in quirk_intel_qat_vf_cap()
5281 state->cap.size = size; in quirk_intel_qat_vf_cap()
5282 cap = (u16 *)&state->cap.data[0]; in quirk_intel_qat_vf_cap()
5290 hlist_add_head(&state->next, &pdev->saved_cap_space); in quirk_intel_qat_vf_cap()
5307 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; in quirk_no_flr()
5317 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); in quirk_no_ext_tags()
5322 bridge->no_ext_tags = 1; in quirk_no_ext_tags()
5325 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); in quirk_no_ext_tags()
5343 if ((pdev->device == 0x7312 && pdev->revision != 0x00) || in quirk_amd_harvest_no_ats()
5344 (pdev->device == 0x7340 && pdev->revision != 0xc5) || in quirk_amd_harvest_no_ats()
5345 (pdev->device == 0x7341 && pdev->revision != 0x00)) in quirk_amd_harvest_no_ats()
5349 pdev->ats_cap = 0; in quirk_amd_harvest_no_ats()
5363 /* Freescale PCIe doesn't support MSI in RC mode */
5367 pdev->no_msi = 1; in quirk_fsl_no_msi()
5372 * Although not allowed by the spec, some multi-function devices have
5385 if (PCI_FUNC(pdev->devfn) != consumer) in pci_create_device_link()
5388 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), in pci_create_device_link()
5389 pdev->bus->number, in pci_create_device_link()
5390 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); in pci_create_device_link()
5391 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { in pci_create_device_link()
5396 if (device_link_add(&pdev->dev, &supplier_pdev->dev, in pci_create_device_link()
5404 pm_runtime_allow(&pdev->dev); in pci_create_device_link()
5414 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); in quirk_gpu_hda()
5437 * Create device link for GPUs with integrated Type-C UCSI controller
5464 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) in quirk_nvidia_hda()
5475 /* The GPU becomes a multi-function device when the HDA is enabled */ in quirk_nvidia_hda()
5477 gpu->multifunction = !!(hdr_type & 0x80); in quirk_nvidia_hda()
5488 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5490 * Item #36 - Downstream port applies ACS Source Validation to Completions
5503 * write, so we do config reads until we receive a non-Config Request Retry
5514 struct pci_dev *bridge = bus->self; in pci_idt_bus_quirk()
5516 pos = bridge->acs_cap; in pci_idt_bus_quirk()
5528 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ in pci_idt_bus_quirk()
5532 /* Re-enable ACS_SV if it was previously enabled */ in pci_idt_bus_quirk()
5572 partition = ioread8(&mmio_ntb->partition_id); in quirk_switchtec_ntb_dma_alias()
5574 partition_map = ioread32(&mmio_ntb->ep_map); in quirk_switchtec_ntb_dma_alias()
5575 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; in quirk_switchtec_ntb_dma_alias()
5576 partition_map &= ~(1ULL << partition); in quirk_switchtec_ntb_dma_alias()
5583 if (!(partition_map & (1ULL << pp))) in quirk_switchtec_ntb_dma_alias()
5590 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); in quirk_switchtec_ntb_dma_alias()
5607 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); in quirk_switchtec_ntb_dma_alias()
5608 devfn = (rid_entry >> 1) & 0xFF; in quirk_switchtec_ntb_dma_alias()
5612 pci_add_dma_alias(pdev, devfn, 1); in quirk_switchtec_ntb_dma_alias()
5708 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5709 pdev->subsystem_device != 0x222e || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5710 !pdev->reset_fn) in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5746 * Device [1b21:2142]
5752 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); in pci_fixup_no_d0_pme()
5762 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
5763 * says "The MSI Function is not implemented on this device" in chapters
5764 * 7.3.27, 7.3.29-7.3.31.
5769 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); in pci_fixup_no_msi_no_pme()
5770 dev->no_msi = 1; in pci_fixup_no_msi_no_pme()
5773 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
5780 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; in apex_pci_fixup_class()
5787 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; in nvidia_ion_ahci_fixup()