Lines Matching refs:pci_regs_behavior
51 struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = { variable
291 bridge->pci_regs_behavior = kmemdup(pci_regs_behavior, in pci_bridge_emul_init()
292 sizeof(pci_regs_behavior), in pci_bridge_emul_init()
294 if (!bridge->pci_regs_behavior) in pci_bridge_emul_init()
307 kfree(bridge->pci_regs_behavior); in pci_bridge_emul_init()
311 bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &= in pci_bridge_emul_init()
313 bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &= in pci_bridge_emul_init()
319 bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &= in pci_bridge_emul_init()
321 bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &= in pci_bridge_emul_init()
324 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &= in pci_bridge_emul_init()
327 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &= in pci_bridge_emul_init()
329 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &= in pci_bridge_emul_init()
334 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0; in pci_bridge_emul_init()
335 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0; in pci_bridge_emul_init()
350 kfree(bridge->pci_regs_behavior); in pci_bridge_emul_cleanup()
387 behavior = bridge->pci_regs_behavior; in pci_bridge_emul_conf_read()
460 behavior = bridge->pci_regs_behavior; in pci_bridge_emul_conf_write()