181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)  in nwl_bridge_writel()  function
315 	nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);  in nwl_pcie_misc_handler()
354 			nwl_bridge_writel(pcie, 1 << bit, status_reg);  in nwl_pcie_handle_msi_irq()
394 	nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);  in nwl_mask_leg_irq()
410 	nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);  in nwl_unmask_leg_irq()
614 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |  in nwl_pcie_enable_msi()
618 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |  in nwl_pcie_enable_msi()
623 	nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);  in nwl_pcie_enable_msi()
624 	nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);  in nwl_pcie_enable_msi()
630 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);  in nwl_pcie_enable_msi()
632 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,  MSGF_MSI_STATUS_HI) &  in nwl_pcie_enable_msi()
635 	nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);  in nwl_pcie_enable_msi()
641 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);  in nwl_pcie_enable_msi()
643 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &  in nwl_pcie_enable_msi()
646 	nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);  in nwl_pcie_enable_msi()
669 	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),  in nwl_pcie_bridge_init()
671 	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),  in nwl_pcie_bridge_init()
675 	nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,  in nwl_pcie_bridge_init()
679 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |  in nwl_pcie_bridge_init()
683 	nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);  in nwl_pcie_bridge_init()
686 	nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,  in nwl_pcie_bridge_init()
700 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |  in nwl_pcie_bridge_init()
703 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |  in nwl_pcie_bridge_init()
707 	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),  in nwl_pcie_bridge_init()
709 	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),  in nwl_pcie_bridge_init()
741 	nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);  in nwl_pcie_bridge_init()
744 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &  in nwl_pcie_bridge_init()
748 	nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);  in nwl_pcie_bridge_init()
752 	nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);  in nwl_pcie_bridge_init()
755 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &  in nwl_pcie_bridge_init()
759 	nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);  in nwl_pcie_bridge_init()
762 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |  in nwl_pcie_bridge_init()