176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)  in nwl_bridge_readl()  function
270 	misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &  in nwl_pcie_misc_handler()
331 	while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &  in nwl_pcie_leg_handler()
352 	while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {  in nwl_pcie_handle_msi_irq()
393 	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);  in nwl_mask_leg_irq()
409 	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);  in nwl_unmask_leg_irq()
606 	ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;  in nwl_pcie_enable_msi()
614 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |  in nwl_pcie_enable_msi()
618 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |  in nwl_pcie_enable_msi()
632 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,  MSGF_MSI_STATUS_HI) &  in nwl_pcie_enable_msi()
643 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &  in nwl_pcie_enable_msi()
662 	breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;  in nwl_pcie_bridge_init()
679 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |  in nwl_pcie_bridge_init()
693 	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;  in nwl_pcie_bridge_init()
700 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |  in nwl_pcie_bridge_init()
703 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |  in nwl_pcie_bridge_init()
713 	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);  in nwl_pcie_bridge_init()
744 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &  in nwl_pcie_bridge_init()
755 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &  in nwl_pcie_bridge_init()
762 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |  in nwl_pcie_bridge_init()