299 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)  in advk_writel()  function
410 	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);  in advk_pcie_train_link()
425 	advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2);  in advk_pcie_train_link()
430 	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);  in advk_pcie_train_link()
464 	advk_writel(pcie, OB_WIN_ENABLE |  in advk_pcie_set_ob_win()
466 	advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));  in advk_pcie_set_ob_win()
467 	advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));  in advk_pcie_set_ob_win()
468 	advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));  in advk_pcie_set_ob_win()
469 	advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));  in advk_pcie_set_ob_win()
470 	advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));  in advk_pcie_set_ob_win()
471 	advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));  in advk_pcie_set_ob_win()
476 	advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));  in advk_pcie_disable_ob_win()
477 	advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));  in advk_pcie_disable_ob_win()
478 	advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));  in advk_pcie_disable_ob_win()
479 	advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));  in advk_pcie_disable_ob_win()
480 	advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num));  in advk_pcie_disable_ob_win()
481 	advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num));  in advk_pcie_disable_ob_win()
482 	advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num));  in advk_pcie_disable_ob_win()
499 	advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG);  in advk_pcie_setup_hw()
505 	advk_writel(pcie, reg, CTRL_CONFIG_REG);  in advk_pcie_setup_hw()
510 	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);  in advk_pcie_setup_hw()
520 	advk_writel(pcie, reg, VENDOR_ID_REG);  in advk_pcie_setup_hw()
540 	advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);  in advk_pcie_setup_hw()
545 	advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);  in advk_pcie_setup_hw()
552 	advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);  in advk_pcie_setup_hw()
562 	advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);  in advk_pcie_setup_hw()
567 	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);  in advk_pcie_setup_hw()
573 	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);  in advk_pcie_setup_hw()
578 	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);  in advk_pcie_setup_hw()
581 	advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);  in advk_pcie_setup_hw()
582 	advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);  in advk_pcie_setup_hw()
583 	advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);  in advk_pcie_setup_hw()
584 	advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);  in advk_pcie_setup_hw()
589 	advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);  in advk_pcie_setup_hw()
591 	advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);  in advk_pcie_setup_hw()
594 	advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);  in advk_pcie_setup_hw()
598 	advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);  in advk_pcie_setup_hw()
612 	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);  in advk_pcie_setup_hw()
619 	advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS);  in advk_pcie_setup_hw()
629 	advk_writel(pcie, reg, PIO_CTRL);  in advk_pcie_setup_hw()
814 		advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG);  in advk_pci_bridge_emul_base_conf_write()
824 			advk_writel(pcie, val, PCIE_CORE_CTRL1_REG);  in advk_pci_bridge_emul_base_conf_write()
904 		advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);  in advk_pci_bridge_emul_pcie_conf_write()
908 		advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);  in advk_pci_bridge_emul_pcie_conf_write()
919 		advk_writel(pcie, val, PCIE_ISR0_MASK_REG);  in advk_pci_bridge_emul_pcie_conf_write()
925 		advk_writel(pcie, new, PCIE_ISR0_REG);  in advk_pci_bridge_emul_pcie_conf_write()
1061 	advk_writel(pcie, reg, PIO_CTRL);  in advk_pcie_rd_conf()
1065 	advk_writel(pcie, reg, PIO_ADDR_LS);  in advk_pcie_rd_conf()
1066 	advk_writel(pcie, 0, PIO_ADDR_MS);  in advk_pcie_rd_conf()
1069 	advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);  in advk_pcie_rd_conf()
1074 		advk_writel(pcie, 1, PIO_ISR);  in advk_pcie_rd_conf()
1075 		advk_writel(pcie, 1, PIO_START);  in advk_pcie_rd_conf()
1142 	advk_writel(pcie, reg, PIO_CTRL);  in advk_pcie_wr_conf()
1146 	advk_writel(pcie, reg, PIO_ADDR_LS);  in advk_pcie_wr_conf()
1147 	advk_writel(pcie, 0, PIO_ADDR_MS);  in advk_pcie_wr_conf()
1155 	advk_writel(pcie, reg, PIO_WR_DATA);  in advk_pcie_wr_conf()
1158 	advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);  in advk_pcie_wr_conf()
1163 		advk_writel(pcie, 1, PIO_ISR);  in advk_pcie_wr_conf()
1164 		advk_writel(pcie, 1, PIO_START);  in advk_pcie_wr_conf()
1249 	advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);  in advk_pcie_irq_mask()
1263 	advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);  in advk_pcie_irq_unmask()
1312 	advk_writel(pcie, lower_32_bits(msi_msg_phys),  in advk_pcie_init_msi_irq_domain()
1314 	advk_writel(pcie, upper_32_bits(msi_msg_phys),  in advk_pcie_init_msi_irq_domain()
1401 		advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);  in advk_pcie_handle_msi()
1406 	advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,  in advk_pcie_handle_msi()
1433 		advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),  in advk_pcie_handle_int()
1453 	advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);  in advk_pcie_irq_handler()