Lines Matching refs:advk_readl
304 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() function
314 val = advk_readl(pcie, CFG_REG); in advk_pcie_ltssm_state()
402 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
417 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
428 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
496 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
502 reg = advk_readl(pcie, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
508 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
537 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
543 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
555 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
570 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
576 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
610 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
627 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_setup_hw()
656 reg = advk_readl(pcie, PIO_STAT); in advk_pcie_check_pio_status()
684 *val = advk_readl(pcie, PIO_RD_DATA); in advk_pcie_check_pio_status()
750 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); in advk_pcie_check_pio_status()
763 start = advk_readl(pcie, PIO_START); in advk_pcie_wait_pio()
764 isr = advk_readl(pcie, PIO_ISR); in advk_pcie_wait_pio()
782 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_read()
793 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) in advk_pci_bridge_emul_base_conf_read()
819 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
846 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_pcie_conf_read()
854 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG); in advk_pci_bridge_emul_pcie_conf_read()
855 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG); in advk_pci_bridge_emul_pcie_conf_read()
863 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
876 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & in advk_pci_bridge_emul_pcie_conf_read()
888 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
915 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) & in advk_pci_bridge_emul_pcie_conf_write()
949 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); in advk_sw_pci_bridge_init()
951 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); in advk_sw_pci_bridge_init()
953 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); in advk_sw_pci_bridge_init()
1016 if (advk_readl(pcie, PIO_START)) { in advk_pcie_pio_is_running()
1055 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_rd_conf()
1136 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_wr_conf()
1247 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1261 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1393 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_pcie_handle_msi()
1394 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1416 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); in advk_pcie_handle_int()
1417 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_handle_int()
1420 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); in advk_pcie_handle_int()
1421 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_handle_int()
1446 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()