54 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_map_bus()  local
76 	return rp->config_axi_slave_base + where;  in mobiveil_pcie_map_bus()
90 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_isr()  local
91 	struct mobiveil_msi *msi = &rp->msi;  in mobiveil_pcie_isr()
117 				virq = irq_find_mapping(rp->intx_domain,  in mobiveil_pcie_isr()
176 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_parse_dt()  local
182 	rp->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);  in mobiveil_pcie_parse_dt()
183 	if (IS_ERR(rp->config_axi_slave_base))  in mobiveil_pcie_parse_dt()
184 		return PTR_ERR(rp->config_axi_slave_base);  in mobiveil_pcie_parse_dt()
185 	rp->ob_io_res = res;  in mobiveil_pcie_parse_dt()
208 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_pcie_enable_msi()
223 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_host_init()  local
224 	struct pci_host_bridge *bridge = rp->bridge;  in mobiveil_host_init()
276 	program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0,  in mobiveil_host_init()
277 			   CFG_WINDOW_TYPE, resource_size(rp->ob_io_res));  in mobiveil_host_init()
311 	struct mobiveil_root_port *rp;  in mobiveil_mask_intx_irq()  local
316 	rp = &pcie->rp;  in mobiveil_mask_intx_irq()
318 	raw_spin_lock_irqsave(&rp->intx_mask_lock, flags);  in mobiveil_mask_intx_irq()
322 	raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags);  in mobiveil_mask_intx_irq()
329 	struct mobiveil_root_port *rp;  in mobiveil_unmask_intx_irq()  local
334 	rp = &pcie->rp;  in mobiveil_unmask_intx_irq()
336 	raw_spin_lock_irqsave(&rp->intx_mask_lock, flags);  in mobiveil_unmask_intx_irq()
340 	raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags);  in mobiveil_unmask_intx_irq()
408 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_irq_msi_domain_alloc()
435 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_irq_msi_domain_free()
456 	struct mobiveil_msi *msi = &pcie->rp.msi;  in mobiveil_allocate_msi_domains()
482 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_init_irq_domain()  local
485 	rp->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,  in mobiveil_pcie_init_irq_domain()
488 	if (!rp->intx_domain) {  in mobiveil_pcie_init_irq_domain()
493 	raw_spin_lock_init(&rp->intx_mask_lock);  in mobiveil_pcie_init_irq_domain()
503 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_integrated_interrupt_init()  local
516 	rp->irq = platform_get_irq(pdev, 0);  in mobiveil_pcie_integrated_interrupt_init()
517 	if (rp->irq < 0)  in mobiveil_pcie_integrated_interrupt_init()
518 		return rp->irq;  in mobiveil_pcie_integrated_interrupt_init()
527 	irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie);  in mobiveil_pcie_integrated_interrupt_init()
539 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_interrupt_init()  local
541 	if (rp->ops->interrupt_init)  in mobiveil_pcie_interrupt_init()
542 		return rp->ops->interrupt_init(pcie);  in mobiveil_pcie_interrupt_init()
559 	struct mobiveil_root_port *rp = &pcie->rp;  in mobiveil_pcie_host_probe()  local
560 	struct pci_host_bridge *bridge = rp->bridge;  in mobiveil_pcie_host_probe()