Lines Matching refs:appl_writel
319 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, in appl_writel() function
379 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0); in tegra_pcie_rp_irq_handler()
384 appl_writel(pcie, val, APPL_CAR_RESET_OVRD); in tegra_pcie_rp_irq_handler()
388 appl_writel(pcie, val, APPL_CAR_RESET_OVRD); in tegra_pcie_rp_irq_handler()
399 appl_writel(pcie, in tegra_pcie_rp_irq_handler()
405 appl_writel(pcie, in tegra_pcie_rp_irq_handler()
443 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); in pex_ep_event_hot_rst_done()
444 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); in pex_ep_event_hot_rst_done()
445 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); in pex_ep_event_hot_rst_done()
446 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); in pex_ep_event_hot_rst_done()
447 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); in pex_ep_event_hot_rst_done()
448 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); in pex_ep_event_hot_rst_done()
449 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); in pex_ep_event_hot_rst_done()
450 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); in pex_ep_event_hot_rst_done()
451 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); in pex_ep_event_hot_rst_done()
452 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); in pex_ep_event_hot_rst_done()
453 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); in pex_ep_event_hot_rst_done()
454 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); in pex_ep_event_hot_rst_done()
455 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); in pex_ep_event_hot_rst_done()
456 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); in pex_ep_event_hot_rst_done()
457 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); in pex_ep_event_hot_rst_done()
458 appl_writel(pcie, 0xFFFFFFFF, APPL_MSI_CTRL_2); in pex_ep_event_hot_rst_done()
462 appl_writel(pcie, val, APPL_CTRL); in pex_ep_event_hot_rst_done()
488 appl_writel(pcie, val, APPL_LTR_MSG_1); in tegra_pcie_ep_irq_thread()
493 appl_writel(pcie, val, APPL_LTR_MSG_2); in tegra_pcie_ep_irq_thread()
521 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0); in tegra_pcie_ep_hard_irq()
539 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_15); in tegra_pcie_ep_hard_irq()
550 appl_writel(pcie, status_l0, APPL_INTR_STATUS_L0); in tegra_pcie_ep_hard_irq()
710 appl_writel(pcie, val, APPL_INTR_EN_L0_0); in tegra_pcie_enable_system_interrupts()
714 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); in tegra_pcie_enable_system_interrupts()
719 appl_writel(pcie, val, APPL_INTR_EN_L0_0); in tegra_pcie_enable_system_interrupts()
724 appl_writel(pcie, val, APPL_INTR_EN_L1_18); in tegra_pcie_enable_system_interrupts()
749 appl_writel(pcie, val, APPL_INTR_EN_L0_0); in tegra_pcie_enable_legacy_interrupts()
757 appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); in tegra_pcie_enable_legacy_interrupts()
772 appl_writel(pcie, val, APPL_INTR_EN_L0_0); in tegra_pcie_enable_msi_interrupts()
781 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); in tegra_pcie_enable_interrupts()
782 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); in tegra_pcie_enable_interrupts()
783 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); in tegra_pcie_enable_interrupts()
784 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); in tegra_pcie_enable_interrupts()
785 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); in tegra_pcie_enable_interrupts()
786 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); in tegra_pcie_enable_interrupts()
787 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); in tegra_pcie_enable_interrupts()
788 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); in tegra_pcie_enable_interrupts()
789 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); in tegra_pcie_enable_interrupts()
790 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); in tegra_pcie_enable_interrupts()
791 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); in tegra_pcie_enable_interrupts()
792 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); in tegra_pcie_enable_interrupts()
793 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); in tegra_pcie_enable_interrupts()
794 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); in tegra_pcie_enable_interrupts()
795 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); in tegra_pcie_enable_interrupts()
907 appl_writel(pcie, val, APPL_PINMUX); in tegra_pcie_prepare_host()
914 appl_writel(pcie, val, APPL_CTRL); in tegra_pcie_prepare_host()
919 appl_writel(pcie, val, APPL_PINMUX); in tegra_pcie_prepare_host()
958 appl_writel(pcie, val, APPL_CTRL); in tegra_pcie_dw_host_init()
1352 appl_writel(pcie, val, APPL_CTRL); in tegra_pcie_config_controller()
1362 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in tegra_pcie_config_controller()
1366 appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE); in tegra_pcie_config_controller()
1368 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE); in tegra_pcie_config_controller()
1371 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL); in tegra_pcie_config_controller()
1375 appl_writel(pcie, val, APPL_CFG_MISC); in tegra_pcie_config_controller()
1381 appl_writel(pcie, val, APPL_PINMUX); in tegra_pcie_config_controller()
1385 appl_writel(pcie, in tegra_pcie_config_controller()
1488 appl_writel(pcie, val, APPL_RADM_STATUS); in tegra_pcie_try_link_l2()
1515 appl_writel(pcie, data, APPL_PINMUX); in tegra_pcie_dw_pme_turnoff()
1530 appl_writel(pcie, data, APPL_CTRL); in tegra_pcie_dw_pme_turnoff()
1542 appl_writel(pcie, data, APPL_PINMUX); in tegra_pcie_dw_pme_turnoff()
1622 appl_writel(pcie, val, APPL_CTRL); in pex_ep_event_pex_rst_assert()
1693 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); in pex_ep_event_pex_rst_deassert()
1694 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); in pex_ep_event_pex_rst_deassert()
1695 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1); in pex_ep_event_pex_rst_deassert()
1696 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2); in pex_ep_event_pex_rst_deassert()
1697 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3); in pex_ep_event_pex_rst_deassert()
1698 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6); in pex_ep_event_pex_rst_deassert()
1699 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7); in pex_ep_event_pex_rst_deassert()
1700 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0); in pex_ep_event_pex_rst_deassert()
1701 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9); in pex_ep_event_pex_rst_deassert()
1702 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10); in pex_ep_event_pex_rst_deassert()
1703 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11); in pex_ep_event_pex_rst_deassert()
1704 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13); in pex_ep_event_pex_rst_deassert()
1705 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14); in pex_ep_event_pex_rst_deassert()
1706 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15); in pex_ep_event_pex_rst_deassert()
1707 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17); in pex_ep_event_pex_rst_deassert()
1713 appl_writel(pcie, val, APPL_DM_TYPE); in pex_ep_event_pex_rst_deassert()
1715 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE); in pex_ep_event_pex_rst_deassert()
1720 appl_writel(pcie, val, APPL_CTRL); in pex_ep_event_pex_rst_deassert()
1725 appl_writel(pcie, val, APPL_CFG_MISC); in pex_ep_event_pex_rst_deassert()
1730 appl_writel(pcie, val, APPL_PINMUX); in pex_ep_event_pex_rst_deassert()
1732 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in pex_ep_event_pex_rst_deassert()
1735 appl_writel(pcie, pcie->atu_dma_res->start & in pex_ep_event_pex_rst_deassert()
1743 appl_writel(pcie, val, APPL_INTR_EN_L0_0); in pex_ep_event_pex_rst_deassert()
1748 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); in pex_ep_event_pex_rst_deassert()
1793 appl_writel(pcie, val, APPL_CTRL); in pex_ep_event_pex_rst_deassert()
1831 appl_writel(pcie, 1, APPL_LEGACY_INTX); in tegra_pcie_ep_raise_legacy_irq()
1833 appl_writel(pcie, 0, APPL_LEGACY_INTX); in tegra_pcie_ep_raise_legacy_irq()
1842 appl_writel(pcie, BIT(irq), APPL_MSI_CTRL_1); in tegra_pcie_ep_raise_msi_irq()
2210 appl_writel(pcie, val, APPL_CTRL); in tegra_pcie_dw_suspend_late()
2274 appl_writel(pcie, val, APPL_CTRL); in tegra_pcie_dw_resume_early()