45 #define APPL_CTRL				0x4  macro
460 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_hot_rst_done()
462 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_hot_rst_done()
912 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_prepare_host()
914 	appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_prepare_host()
956 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_host_init()
958 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_host_init()
1348 		val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_config_controller()
1352 		appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_config_controller()
1370 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_config_controller()
1371 	appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);  in tegra_pcie_config_controller()
1528 			data = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_pme_turnoff()
1530 			appl_writel(pcie, data, APPL_CTRL);  in tegra_pcie_dw_pme_turnoff()
1620 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_assert()
1622 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_assert()
1717 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1720 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1791 	val = appl_readl(pcie, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
1793 	appl_writel(pcie, val, APPL_CTRL);  in pex_ep_event_pex_rst_deassert()
2206 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_suspend_late()
2210 	appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_suspend_late()
2268 	val = appl_readl(pcie, APPL_CTRL);  in tegra_pcie_dw_resume_early()
2274 	appl_writel(pcie, val, APPL_CTRL);  in tegra_pcie_dw_resume_early()