Lines Matching full:pci
31 #include <linux/pci.h>
43 #include <linux/pci-epf.h>
46 #include "../../pci.h"
155 struct dw_pcie *pci; member
250 dev_err(rk_pcie->pci->dev, "Read APB address failed\n"); in __rk_pcie_read_apb()
262 dev_err(rk_pcie->pci->dev, "Write APB address failed\n"); in __rk_pcie_write_apb()
276 static u8 rk_pcie_iatu_unroll_enabled(struct dw_pcie *pci) in rk_pcie_iatu_unroll_enabled() argument
280 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); in rk_pcie_iatu_unroll_enabled()
287 static void rk_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) in rk_pcie_writel_atu() argument
291 if (pci->ops->write_dbi) { in rk_pcie_writel_atu()
292 pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val); in rk_pcie_writel_atu()
296 ret = dw_pcie_write(pci->atu_base + reg, 4, val); in rk_pcie_writel_atu()
298 dev_err(pci->dev, "Write ATU address failed\n"); in rk_pcie_writel_atu()
301 static void rk_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg, in rk_pcie_writel_ib_unroll() argument
306 rk_pcie_writel_atu(pci, offset + reg, val); in rk_pcie_writel_ib_unroll()
309 static u32 rk_pcie_readl_atu(struct dw_pcie *pci, u32 reg) in rk_pcie_readl_atu() argument
314 if (pci->ops->read_dbi) in rk_pcie_readl_atu()
315 return pci->ops->read_dbi(pci, pci->atu_base, reg, 4); in rk_pcie_readl_atu()
317 ret = dw_pcie_read(pci->atu_base + reg, 4, &val); in rk_pcie_readl_atu()
319 dev_err(pci->dev, "Read ATU address failed\n"); in rk_pcie_readl_atu()
324 static u32 rk_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg) in rk_pcie_readl_ib_unroll() argument
328 return rk_pcie_readl_atu(pci, offset + reg); in rk_pcie_readl_ib_unroll()
331 static int rk_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, u8 func_no, in rk_pcie_prog_inbound_atu_unroll() argument
338 rk_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, in rk_pcie_prog_inbound_atu_unroll()
340 rk_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, in rk_pcie_prog_inbound_atu_unroll()
354 rk_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type | in rk_pcie_prog_inbound_atu_unroll()
356 rk_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, in rk_pcie_prog_inbound_atu_unroll()
366 val = rk_pcie_readl_ib_unroll(pci, index, in rk_pcie_prog_inbound_atu_unroll()
373 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in rk_pcie_prog_inbound_atu_unroll()
379 static int rk_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, in rk_pcie_prog_inbound_atu() argument
386 if (pci->iatu_unroll_enabled) in rk_pcie_prog_inbound_atu()
387 return rk_pcie_prog_inbound_atu_unroll(pci, func_no, index, bar, in rk_pcie_prog_inbound_atu()
390 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND | in rk_pcie_prog_inbound_atu()
392 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr)); in rk_pcie_prog_inbound_atu()
393 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr)); in rk_pcie_prog_inbound_atu()
406 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type | in rk_pcie_prog_inbound_atu()
408 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE | in rk_pcie_prog_inbound_atu()
417 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); in rk_pcie_prog_inbound_atu()
423 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in rk_pcie_prog_inbound_atu()
442 dev_err(rk_pcie->pci->dev, "No free inbound window\n"); in rk_pcie_ep_inbound_atu()
447 ret = rk_pcie_prog_inbound_atu(rk_pcie->pci, func_no, free_win, bar, in rk_pcie_ep_inbound_atu()
450 dev_err(rk_pcie->pci->dev, "Failed to program IB window\n"); in rk_pcie_ep_inbound_atu()
463 static void rk_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg, in rk_pcie_writel_ob_unroll() argument
468 rk_pcie_writel_atu(pci, offset + reg, val); in rk_pcie_writel_ob_unroll()
471 static u32 rk_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) in rk_pcie_readl_ob_unroll() argument
475 return rk_pcie_readl_atu(pci, offset + reg); in rk_pcie_readl_ob_unroll()
478 static void rk_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no, in rk_pcie_prog_outbound_atu_unroll() argument
486 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, in rk_pcie_prog_outbound_atu_unroll()
488 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, in rk_pcie_prog_outbound_atu_unroll()
490 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_LIMIT, in rk_pcie_prog_outbound_atu_unroll()
492 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT, in rk_pcie_prog_outbound_atu_unroll()
494 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, in rk_pcie_prog_outbound_atu_unroll()
496 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, in rk_pcie_prog_outbound_atu_unroll()
498 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, in rk_pcie_prog_outbound_atu_unroll()
500 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, in rk_pcie_prog_outbound_atu_unroll()
508 val = rk_pcie_readl_ob_unroll(pci, index, in rk_pcie_prog_outbound_atu_unroll()
515 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in rk_pcie_prog_outbound_atu_unroll()
518 static void rk_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, in rk_pcie_prog_outbound_atu() argument
523 if (pci->ops->cpu_addr_fixup) in rk_pcie_prog_outbound_atu()
524 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); in rk_pcie_prog_outbound_atu()
526 if (pci->iatu_unroll_enabled) { in rk_pcie_prog_outbound_atu()
527 rk_pcie_prog_outbound_atu_unroll(pci, 0x0, index, type, in rk_pcie_prog_outbound_atu()
532 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, in rk_pcie_prog_outbound_atu()
534 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE, in rk_pcie_prog_outbound_atu()
536 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE, in rk_pcie_prog_outbound_atu()
538 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT, in rk_pcie_prog_outbound_atu()
540 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, in rk_pcie_prog_outbound_atu()
542 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, in rk_pcie_prog_outbound_atu()
544 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type | in rk_pcie_prog_outbound_atu()
546 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE); in rk_pcie_prog_outbound_atu()
553 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); in rk_pcie_prog_outbound_atu()
559 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in rk_pcie_prog_outbound_atu()
575 dev_err(rk_pcie->pci->dev, "No free outbound window\n"); in rk_pcie_ep_outbound_atu()
580 rk_pcie_prog_outbound_atu(rk_pcie->pci, free_win, PCIE_ATU_TYPE_MEM, in rk_pcie_ep_outbound_atu()
598 dw_pcie_writel_dbi(rk_pcie->pci, reg, 0x0); in __rk_pcie_ep_reset_bar()
600 dw_pcie_writel_dbi(rk_pcie->pci, reg + 4, 0x0); in __rk_pcie_ep_reset_bar()
642 val = dw_pcie_find_ext_capability(rk_pcie->pci, PCI_EXT_CAP_ID_L1SS); in disable_aspm_l1ss()
644 dev_err(rk_pcie->pci->dev, "can't find l1ss cap\n"); in disable_aspm_l1ss()
651 val = dw_pcie_readl_dbi(rk_pcie->pci, cfg_link_cap_l1sub); in disable_aspm_l1ss()
653 dw_pcie_writel_dbi(rk_pcie->pci, cfg_link_cap_l1sub, val); in disable_aspm_l1ss()
681 dw_pcie_writel_dbi(rk_pcie->pci, in rk_pcie_set_mode()
703 static int rk_pcie_link_up(struct dw_pcie *pci) in rk_pcie_link_up() argument
705 struct rk_pcie *rk_pcie = to_rk_pcie(pci); in rk_pcie_link_up()
744 struct dw_pcie *pci = rk_pcie->pci; in rk_pcie_debug_dump() local
746 dev_info(pci->dev, "ltssm = 0x%x\n", in rk_pcie_debug_dump()
749 dev_info(pci->dev, "fifo_status = 0x%x\n", in rk_pcie_debug_dump()
754 static int rk_pcie_establish_link(struct dw_pcie *pci) in rk_pcie_establish_link() argument
757 struct rk_pcie *rk_pcie = to_rk_pcie(pci); in rk_pcie_establish_link()
765 if (dw_pcie_link_up(pci) && !std_rc) { in rk_pcie_establish_link()
766 dev_err(pci->dev, "link is already up\n"); in rk_pcie_establish_link()
801 * minimum of 100ms. See table 2-4 in section 2.6.2 AC, the PCI Express in rk_pcie_establish_link()
816 if (dw_pcie_link_up(pci)) { in rk_pcie_establish_link()
826 if (dw_pcie_link_up(pci)) { in rk_pcie_establish_link()
827 dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n", in rk_pcie_establish_link()
834 dev_info_ratelimited(pci->dev, "PCIe Linking... LTSSM is 0x%x\n", in rk_pcie_establish_link()
840 dev_err(pci->dev, "PCIe Link Fail\n"); in rk_pcie_establish_link()
847 return dw_pcie_readl_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + in rk_pcie_udma_enabled()
856 rk_pcie->dma_obj = rk_pcie_dma_obj_probe(rk_pcie->pci->dev); in rk_pcie_init_dma_trx()
858 dev_err(rk_pcie->pci->dev, "failed to prepare dma object\n"); in rk_pcie_init_dma_trx()
864 rk_pcie->dma_obj = pcie_dw_dmatest_register(rk_pcie->pci->dev, true); in rk_pcie_init_dma_trx()
866 dev_err(rk_pcie->pci->dev, "failed to prepare dmatest\n"); in rk_pcie_init_dma_trx()
874 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_INT_MASK, in rk_pcie_init_dma_trx()
877 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_INT_MASK, in rk_pcie_init_dma_trx()
893 header = dw_pcie_readl_dbi(rk_pcie->pci, pos); in rk_pci_find_resbar_capability()
910 header = dw_pcie_readl_dbi(rk_pcie->pci, pos); in rk_pci_find_resbar_capability()
919 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) in dw_pcie_write_dbi2() argument
923 if (pci->ops && pci->ops->write_dbi2) { in dw_pcie_write_dbi2()
924 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); in dw_pcie_write_dbi2()
928 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); in dw_pcie_write_dbi2()
930 dev_err(pci->dev, "write DBI address failed\n"); in dw_pcie_write_dbi2()
943 dw_pcie_writel_dbi2(rk_pcie->pci, reg + 4, 0); in rk_pcie_ep_set_bar_flag()
945 dw_pcie_writel_dbi(rk_pcie->pci, reg, flags); in rk_pcie_ep_set_bar_flag()
947 dw_pcie_writel_dbi(rk_pcie->pci, reg + 4, 0); in rk_pcie_ep_set_bar_flag()
957 struct device *dev = rk_pcie->pci->dev; in rk_pcie_ep_setup()
966 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_INT_MASK, in rk_pcie_ep_setup()
969 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_INT_MASK, in rk_pcie_ep_setup()
977 val = dw_pcie_readl_dbi(rk_pcie->pci, PCIE_PORT_LINK_CONTROL); in rk_pcie_ep_setup()
997 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_PORT_LINK_CONTROL, val); in rk_pcie_ep_setup()
1000 val = dw_pcie_readl_dbi(rk_pcie->pci, PCIE_LINK_WIDTH_SPEED_CONTROL); in rk_pcie_ep_setup()
1019 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); in rk_pcie_ep_setup()
1022 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_TYPE0_STATUS_COMMAND_REG, 0x6); in rk_pcie_ep_setup()
1029 dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x4, 0xfffff0); in rk_pcie_ep_setup()
1030 dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x8, 0x13c0); in rk_pcie_ep_setup()
1031 dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0xc, 0xfffff0); in rk_pcie_ep_setup()
1032 dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x10, 0x3c0); in rk_pcie_ep_setup()
1034 dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0); in rk_pcie_ep_setup()
1035 dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x8 + bar * 0x8, 0x6c0); in rk_pcie_ep_setup()
1046 dw_pcie_writew_dbi(rk_pcie->pci, PCI_DEVICE_ID, 0x356a); in rk_pcie_ep_setup()
1047 dw_pcie_writew_dbi(rk_pcie->pci, PCI_CLASS_DEVICE, 0x0580); in rk_pcie_ep_setup()
1052 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_SB_BAR0_MASK_REG, val); in rk_pcie_ep_setup()
1060 struct device *dev = rk_pcie->pci->dev; in rk_pcie_ep_win_parse()
1116 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in rk_pcie_msi_set_num_vectors() local
1117 struct rk_pcie *rk_pcie = to_rk_pcie(pci); in rk_pcie_msi_set_num_vectors()
1125 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in rk_pcie_host_init() local
1130 dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_0 * 4, 0); in rk_pcie_host_init()
1131 dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_1 * 4, 0); in rk_pcie_host_init()
1133 ret = rk_pcie_establish_link(pci); in rk_pcie_host_init()
1148 struct dw_pcie *pci = rk_pcie->pci; in rk_add_pcie_port() local
1149 struct pcie_port *pp = &pci->pp; in rk_add_pcie_port()
1150 struct device *dev = pci->dev; in rk_add_pcie_port()
1178 struct device *dev = rk_pcie->pci->dev; in rk_pcie_add_ep()
1204 rk_pcie->pci->dbi_base2 = rk_pcie->pci->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET; in rk_pcie_add_ep()
1205 rk_pcie->pci->atu_base = rk_pcie->pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; in rk_pcie_add_ep()
1206 rk_pcie->pci->iatu_unroll_enabled = rk_pcie_iatu_unroll_enabled(rk_pcie->pci); in rk_pcie_add_ep()
1216 ret = rk_pcie_establish_link(rk_pcie->pci); in rk_pcie_add_ep()
1230 struct device *dev = rk_pcie->pci->dev; in rk_pcie_clk_init()
1263 rk_pcie->pci->dbi_base = rk_pcie->dbi_base; in rk_pcie_resource_get()
1304 struct device *dev = rk_pcie->pci->dev; in rk_pcie_phy_init()
1365 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_ENB, in rk_pcie_start_dma_rd()
1367 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_CTRL_LO, in rk_pcie_start_dma_rd()
1369 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_CTRL_HI, in rk_pcie_start_dma_rd()
1371 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_XFERSIZE, in rk_pcie_start_dma_rd()
1373 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_SAR_PTR_LO, in rk_pcie_start_dma_rd()
1375 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_SAR_PTR_HI, in rk_pcie_start_dma_rd()
1377 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_DAR_PTR_LO, in rk_pcie_start_dma_rd()
1379 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_RD_DAR_PTR_HI, in rk_pcie_start_dma_rd()
1381 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_DOORBELL, in rk_pcie_start_dma_rd()
1389 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_ENB, in rk_pcie_start_dma_wr()
1391 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_CTRL_LO, in rk_pcie_start_dma_wr()
1393 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_CTRL_HI, in rk_pcie_start_dma_wr()
1395 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_XFERSIZE, in rk_pcie_start_dma_wr()
1397 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_SAR_PTR_LO, in rk_pcie_start_dma_wr()
1399 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_SAR_PTR_HI, in rk_pcie_start_dma_wr()
1401 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_DAR_PTR_LO, in rk_pcie_start_dma_wr()
1403 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_DAR_PTR_HI, in rk_pcie_start_dma_wr()
1405 dw_pcie_writel_dbi(rk_pcie->pci, ctr_off + PCIE_DMA_WR_WEILO, in rk_pcie_start_dma_wr()
1407 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_DOORBELL, in rk_pcie_start_dma_wr()
1455 val = dw_pcie_readl_dbi(rk_pcie->pci, PCI_COMMAND); in rk_pcie_hot_rst_work()
1459 dw_pcie_writel_dbi(rk_pcie->pci, PCI_COMMAND, val); in rk_pcie_hot_rst_work()
1465 dev_err(rk_pcie->pci->dev, "wait for detect quiet failed!\n"); in rk_pcie_hot_rst_work()
1480 status.asdword = dw_pcie_readl_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + in rk_pcie_sys_irq_handler()
1485 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + in rk_pcie_sys_irq_handler()
1492 dev_err(rk_pcie->pci->dev, "%s, abort\n", __func__); in rk_pcie_sys_irq_handler()
1494 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + in rk_pcie_sys_irq_handler()
1499 status.asdword = dw_pcie_readl_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + in rk_pcie_sys_irq_handler()
1504 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + in rk_pcie_sys_irq_handler()
1511 dev_err(rk_pcie->pci->dev, "%s, abort\n", __func__); in rk_pcie_sys_irq_handler()
1513 dw_pcie_writel_dbi(rk_pcie->pci, PCIE_DMA_OFFSET + in rk_pcie_sys_irq_handler()
1535 dev_err(rk_pcie->pci->dev, "missing sys IRQ resource\n"); in rk_pcie_request_sys_irq()
1539 ret = devm_request_irq(rk_pcie->pci->dev, irq, rk_pcie_sys_irq_handler, in rk_pcie_request_sys_irq()
1542 dev_err(rk_pcie->pci->dev, "failed to request PCIe subsystem IRQ\n"); in rk_pcie_request_sys_irq()
1608 struct device *dev = rk_pcie->pci->dev; in rk1808_pcie_fixup()
1697 struct device *dev = rockchip->pci->dev; in rk_pcie_legacy_int_handler()
1723 struct device *dev = rockchip->pci->dev; in rk_pcie_init_irq_domain()
1745 struct device *dev = rk_pcie->pci->dev; in rk_pcie_enable_power()
1760 struct device *dev = rk_pcie->pci->dev; in rk_pcie_disable_power()
1774 dw_pcie_writel_dbi(pcie->pci, cap_base + 8, v); \
1775 seq_printf(s, ss "0x%x\n", dw_pcie_readl_dbi(pcie->pci, cap_base + 0xc)); \
1802 cap_base = dw_pcie_find_ext_capability(pcie->pci, PCI_EXT_CAP_ID_VNDR); in rockchip_pcie_rasdes_show()
1804 dev_err(pcie->pci->dev, "Not able to find RASDES CAP!\n"); in rockchip_pcie_rasdes_show()
1856 cap_base = dw_pcie_find_ext_capability(pcie->pci, PCI_EXT_CAP_ID_VNDR); in rockchip_pcie_rasdes_write()
1858 dev_err(pcie->pci->dev, "Not able to find RASDES CAP!\n"); in rockchip_pcie_rasdes_write()
1863 dev_info(pcie->pci->dev, "RAS DES Event: Enable ALL!\n"); in rockchip_pcie_rasdes_write()
1864 dw_pcie_writel_dbi(pcie->pci, cap_base + 8, 0x1c); in rockchip_pcie_rasdes_write()
1865 dw_pcie_writel_dbi(pcie->pci, cap_base + 8, 0x3); in rockchip_pcie_rasdes_write()
1867 dev_info(pcie->pci->dev, "RAS DES Event: disable ALL!\n"); in rockchip_pcie_rasdes_write()
1868 dw_pcie_writel_dbi(pcie->pci, cap_base + 8, 0x14); in rockchip_pcie_rasdes_write()
1870 dev_info(pcie->pci->dev, "RAS DES Event: Clear ALL!\n"); in rockchip_pcie_rasdes_write()
1871 dw_pcie_writel_dbi(pcie->pci, cap_base + 8, 0x3); in rockchip_pcie_rasdes_write()
1873 dev_info(pcie->pci->dev, "Not support command!\n"); in rockchip_pcie_rasdes_write()
1910 pcie->debugfs = debugfs_create_dir(dev_name(pcie->pci->dev), NULL); in rockchip_pcie_debugfs_init()
1914 debugfs_create_devm_seqfile(pcie->pci->dev, "dumpfifo", in rockchip_pcie_debugfs_init()
1935 struct dw_pcie *pci; in rk_pcie_really_probe() local
1959 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); in rk_pcie_really_probe()
1960 if (!pci) { in rk_pcie_really_probe()
1965 pci->dev = dev; in rk_pcie_really_probe()
1966 pci->ops = &dw_pcie_ops; in rk_pcie_really_probe()
1970 rk_pcie->pci = pci; in rk_pcie_really_probe()
2048 dw_pcie_dbi_ro_wr_en(pci); in rk_pcie_really_probe()
2078 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); in rk_pcie_really_probe()
2080 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); in rk_pcie_really_probe()
2086 val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS); in rk_pcie_really_probe()
2088 dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val); in rk_pcie_really_probe()
2137 dw_pcie_dbi_ro_wr_dis(pci); in rk_pcie_really_probe()
2150 val = dw_pcie_find_ext_capability(rk_pcie->pci, PCI_EXT_CAP_ID_VNDR); in rk_pcie_really_probe()
2156 dw_pcie_writel_dbi(rk_pcie->pci, val + 8, 0x1c); in rk_pcie_really_probe()
2157 dw_pcie_writel_dbi(rk_pcie->pci, val + 8, 0x3); in rk_pcie_really_probe()
2201 struct pcie_port *pp = &rk_pcie->pci->pp; in rk_pcie_downstream_dev_to_d0()
2216 dev_err(rk_pcie->pci->dev, "Failed to find downstream devices\n"); in rk_pcie_downstream_dev_to_d0()
2223 dw_pcie_writel_dbi(rk_pcie->pci, bridge->l1ss + PCI_L1SS_CTL1, rk_pcie->l1ss_ctl1); in rk_pcie_downstream_dev_to_d0()
2226 dw_pcie_writel_dbi(rk_pcie->pci, bridge->pcie_cap + PCI_EXP_LNKCTL, rk_pcie->aspm); in rk_pcie_downstream_dev_to_d0()
2228 val = dw_pcie_readl_dbi(rk_pcie->pci, bridge->l1ss + PCI_L1SS_CTL1); in rk_pcie_downstream_dev_to_d0()
2234 val = dw_pcie_readl_dbi(rk_pcie->pci, bridge->pcie_cap + PCI_EXP_LNKCTL); in rk_pcie_downstream_dev_to_d0()
2237 dw_pcie_writel_dbi(rk_pcie->pci, bridge->pcie_cap + PCI_EXP_LNKCTL, val); in rk_pcie_downstream_dev_to_d0()
2243 dev_err(rk_pcie->pci->dev, in rk_pcie_downstream_dev_to_d0()
2268 struct dw_pcie *pci = rk_pcie->pci; in rockchip_dw_pcie_suspend() local
2272 * This is as per PCI Express Base r5.0 r1.0 May 22-2019, in rockchip_dw_pcie_suspend()
2292 dw_pcie_dbi_ro_wr_dis(rk_pcie->pci); in rockchip_dw_pcie_suspend()
2336 dev_err(pci->dev, "Link isn't in L2 idle!\n"); in rockchip_dw_pcie_suspend()
2394 dw_pcie_dbi_ro_wr_en(rk_pcie->pci); in rockchip_dw_pcie_resume()
2409 dw_pcie_setup_rc(&rk_pcie->pci->pp); in rockchip_dw_pcie_resume()
2411 ret = rk_pcie_establish_link(rk_pcie->pci); in rockchip_dw_pcie_resume()
2431 dw_pcie_dbi_ro_wr_dis(rk_pcie->pci); in rockchip_dw_pcie_resume()
2439 if (rk_pcie->pci->pp.msi_irq > 0) in rockchip_dw_pcie_resume()
2440 dw_pcie_msi_init(&rk_pcie->pci->pp); in rockchip_dw_pcie_resume()
2454 dw_pcie_dbi_ro_wr_en(rk_pcie->pci); in rockchip_dw_pcie_prepare()
2456 dw_pcie_dbi_ro_wr_dis(rk_pcie->pci); in rockchip_dw_pcie_prepare()
2465 dw_pcie_dbi_ro_wr_en(rk_pcie->pci); in rockchip_dw_pcie_complete()
2467 dw_pcie_dbi_ro_wr_dis(rk_pcie->pci); in rockchip_dw_pcie_complete()