controller/dwc/pcie-dw-dmatest.c

22 static int test_size = 0x20;
32 …E_PARM_DESC(chn_en, "Each bits for one dma channel, up to 2 channels, (default enable channel 0)");
38 static unsigned int bus_addr = 0x3c000000;
40 …RM_DESC(bus_addr, "Dmatest chn0 bus_addr(remote), chn1 add offset 0x100000, (default 0x3c000000)");
42 static unsigned int local_addr = 0x3c000000;
44 …DESC(local_addr, "Dmatest chn0 local_addr(local), chn1 add offset 0x100000, (default 0x3c000000)");
48 MODULE_PARM_DESC(test_dev, "Choose dma_obj device,(default 0)");
76 	for (i = 0; i < PCIE_DW_MISC_DMATEST_DEV_MAX; i++) {  in pcie_dw_dmatest_show()
126 		if (ret < 0)  in rk_pcie_ep_dma_frombus()
128 		else if (ret == 0)  in rk_pcie_ep_dma_frombus()
169 		if (ret < 0)  in rk_pcie_ep_dma_tobus()
171 		else if (ret == 0)  in rk_pcie_ep_dma_tobus()
207 	return 0;  in rk_pcie_dma_interrupt_handler_call_back()
226 	for (i = 0; i < PCIE_DMA_CHANEL_MAX_NUM; i++) {  in pcie_dw_dmatest_register()
248 	long long us = 0;  in dma_test()
260 	for (i = 0; i < loop; i++) {  in dma_test()
286 	return 0;  in dma_test()
291 	dma_test(&s_dmatest_dev[test_dev], 0, bus_addr, local_addr, test_size,  in dma_test_ch0()
292 		 cycles_count, rw_test & 0x1, (rw_test & 0x2) >> 1);  in dma_test_ch0()
294 	return 0;  in dma_test_ch0()
302 			 cycles_count, rw_test & 0x1, (rw_test & 0x2) >> 1);  in dma_test_ch1()
305 			 cycles_count, rw_test & 0x1, (rw_test & 0x2) >> 1);  in dma_test_ch1()
307 	return 0;  in dma_test_ch1()
321 	return 0;  in dma_run()
328 	if (!s_dmatest_dev[0].obj) {  in pcie_dw_dmatest()
344 	return 0;  in pcie_dw_dmatest()