Lines Matching full:pci
16 #include "../../pci.h"
21 * are for configuring host controllers, which are bridges *to* PCI devices but
22 * are not PCI devices themselves.
24 static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, in __dw_pcie_find_next_cap() argument
33 reg = dw_pcie_readw_dbi(pci, cap_ptr); in __dw_pcie_find_next_cap()
43 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); in __dw_pcie_find_next_cap()
46 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) in dw_pcie_find_capability() argument
51 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); in dw_pcie_find_capability()
54 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); in dw_pcie_find_capability()
58 static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, in dw_pcie_find_next_ext_capability() argument
71 header = dw_pcie_readl_dbi(pci, pos); in dw_pcie_find_next_ext_capability()
87 header = dw_pcie_readl_dbi(pci, pos); in dw_pcie_find_next_ext_capability()
93 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) in dw_pcie_find_ext_capability() argument
95 return dw_pcie_find_next_ext_capability(pci, 0, cap); in dw_pcie_find_ext_capability()
139 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) in dw_pcie_read_dbi() argument
144 if (pci->ops->read_dbi) in dw_pcie_read_dbi()
145 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); in dw_pcie_read_dbi()
147 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); in dw_pcie_read_dbi()
149 dev_err(pci->dev, "Read DBI address failed\n"); in dw_pcie_read_dbi()
155 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) in dw_pcie_write_dbi() argument
159 if (pci->ops->write_dbi) { in dw_pcie_write_dbi()
160 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); in dw_pcie_write_dbi()
164 ret = dw_pcie_write(pci->dbi_base + reg, size, val); in dw_pcie_write_dbi()
166 dev_err(pci->dev, "Write DBI address failed\n"); in dw_pcie_write_dbi()
170 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) in dw_pcie_write_dbi2() argument
174 if (pci->ops->write_dbi2) { in dw_pcie_write_dbi2()
175 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); in dw_pcie_write_dbi2()
179 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); in dw_pcie_write_dbi2()
181 dev_err(pci->dev, "write DBI address failed\n"); in dw_pcie_write_dbi2()
184 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg) in dw_pcie_readl_atu() argument
189 if (pci->ops->read_dbi) in dw_pcie_readl_atu()
190 return pci->ops->read_dbi(pci, pci->atu_base, reg, 4); in dw_pcie_readl_atu()
192 ret = dw_pcie_read(pci->atu_base + reg, 4, &val); in dw_pcie_readl_atu()
194 dev_err(pci->dev, "Read ATU address failed\n"); in dw_pcie_readl_atu()
199 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) in dw_pcie_writel_atu() argument
203 if (pci->ops->write_dbi) { in dw_pcie_writel_atu()
204 pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val); in dw_pcie_writel_atu()
208 ret = dw_pcie_write(pci->atu_base + reg, 4, val); in dw_pcie_writel_atu()
210 dev_err(pci->dev, "Write ATU address failed\n"); in dw_pcie_writel_atu()
213 static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) in dw_pcie_readl_ob_unroll() argument
217 return dw_pcie_readl_atu(pci, offset + reg); in dw_pcie_readl_ob_unroll()
220 static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg, in dw_pcie_writel_ob_unroll() argument
225 dw_pcie_writel_atu(pci, offset + reg, val); in dw_pcie_writel_ob_unroll()
228 static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no, in dw_pcie_prog_outbound_atu_unroll() argument
236 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, in dw_pcie_prog_outbound_atu_unroll()
238 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, in dw_pcie_prog_outbound_atu_unroll()
240 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_LIMIT, in dw_pcie_prog_outbound_atu_unroll()
242 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT, in dw_pcie_prog_outbound_atu_unroll()
244 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, in dw_pcie_prog_outbound_atu_unroll()
246 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, in dw_pcie_prog_outbound_atu_unroll()
248 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, in dw_pcie_prog_outbound_atu_unroll()
250 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, in dw_pcie_prog_outbound_atu_unroll()
258 val = dw_pcie_readl_ob_unroll(pci, index, in dw_pcie_prog_outbound_atu_unroll()
265 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in dw_pcie_prog_outbound_atu_unroll()
268 static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, in __dw_pcie_prog_outbound_atu() argument
274 if (pci->ops->cpu_addr_fixup) in __dw_pcie_prog_outbound_atu()
275 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); in __dw_pcie_prog_outbound_atu()
277 if (pci->iatu_unroll_enabled & DWC_IATU_UNROLL_EN) { in __dw_pcie_prog_outbound_atu()
278 dw_pcie_prog_outbound_atu_unroll(pci, func_no, index, type, in __dw_pcie_prog_outbound_atu()
283 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, in __dw_pcie_prog_outbound_atu()
285 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE, in __dw_pcie_prog_outbound_atu()
287 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE, in __dw_pcie_prog_outbound_atu()
289 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT, in __dw_pcie_prog_outbound_atu()
291 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, in __dw_pcie_prog_outbound_atu()
293 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, in __dw_pcie_prog_outbound_atu()
295 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type | in __dw_pcie_prog_outbound_atu()
297 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE); in __dw_pcie_prog_outbound_atu()
304 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); in __dw_pcie_prog_outbound_atu()
310 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in __dw_pcie_prog_outbound_atu()
313 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, in dw_pcie_prog_outbound_atu() argument
316 __dw_pcie_prog_outbound_atu(pci, 0, index, type, in dw_pcie_prog_outbound_atu()
320 void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, in dw_pcie_prog_ep_outbound_atu() argument
324 __dw_pcie_prog_outbound_atu(pci, func_no, index, type, in dw_pcie_prog_ep_outbound_atu()
328 static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg) in dw_pcie_readl_ib_unroll() argument
332 return dw_pcie_readl_atu(pci, offset + reg); in dw_pcie_readl_ib_unroll()
335 static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg, in dw_pcie_writel_ib_unroll() argument
340 dw_pcie_writel_atu(pci, offset + reg, val); in dw_pcie_writel_ib_unroll()
343 static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, u8 func_no, in dw_pcie_prog_inbound_atu_unroll() argument
350 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, in dw_pcie_prog_inbound_atu_unroll()
352 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, in dw_pcie_prog_inbound_atu_unroll()
366 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type | in dw_pcie_prog_inbound_atu_unroll()
368 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, in dw_pcie_prog_inbound_atu_unroll()
378 val = dw_pcie_readl_ib_unroll(pci, index, in dw_pcie_prog_inbound_atu_unroll()
385 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_inbound_atu_unroll()
390 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, in dw_pcie_prog_inbound_atu() argument
397 if (pci->iatu_unroll_enabled & DWC_IATU_UNROLL_EN) in dw_pcie_prog_inbound_atu()
398 return dw_pcie_prog_inbound_atu_unroll(pci, func_no, index, bar, in dw_pcie_prog_inbound_atu()
401 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND | in dw_pcie_prog_inbound_atu()
403 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr)); in dw_pcie_prog_inbound_atu()
404 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr)); in dw_pcie_prog_inbound_atu()
417 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type | in dw_pcie_prog_inbound_atu()
419 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE | in dw_pcie_prog_inbound_atu()
428 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); in dw_pcie_prog_inbound_atu()
434 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_inbound_atu()
439 void dw_pcie_disable_atu(struct dw_pcie *pci, int index, in dw_pcie_disable_atu() argument
455 if (pci->iatu_unroll_enabled) { in dw_pcie_disable_atu()
457 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, in dw_pcie_disable_atu()
460 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, in dw_pcie_disable_atu()
464 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index); in dw_pcie_disable_atu()
465 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE); in dw_pcie_disable_atu()
469 int dw_pcie_wait_for_link(struct dw_pcie *pci) in dw_pcie_wait_for_link() argument
475 if (dw_pcie_link_up(pci)) { in dw_pcie_wait_for_link()
476 dev_info(pci->dev, "Link up\n"); in dw_pcie_wait_for_link()
482 dev_info(pci->dev, "Phy link never came up\n"); in dw_pcie_wait_for_link()
488 int dw_pcie_link_up(struct dw_pcie *pci) in dw_pcie_link_up() argument
492 if (pci->ops->link_up) in dw_pcie_link_up()
493 return pci->ops->link_up(pci); in dw_pcie_link_up()
495 val = readl(pci->dbi_base + PCIE_PORT_DEBUG1); in dw_pcie_link_up()
501 void dw_pcie_upconfig_setup(struct dw_pcie *pci) in dw_pcie_upconfig_setup() argument
505 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL); in dw_pcie_upconfig_setup()
507 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val); in dw_pcie_upconfig_setup()
511 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) in dw_pcie_link_set_max_speed() argument
514 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); in dw_pcie_link_set_max_speed()
516 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); in dw_pcie_link_set_max_speed()
517 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); in dw_pcie_link_set_max_speed()
540 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed); in dw_pcie_link_set_max_speed()
543 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); in dw_pcie_link_set_max_speed()
547 static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) in dw_pcie_iatu_unroll_enabled() argument
551 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); in dw_pcie_iatu_unroll_enabled()
558 void dw_pcie_setup(struct dw_pcie *pci) in dw_pcie_setup() argument
561 struct device *dev = pci->dev; in dw_pcie_setup()
565 if (pci->version >= 0x480A || (!pci->version && in dw_pcie_setup()
566 dw_pcie_iatu_unroll_enabled(pci))) { in dw_pcie_setup()
567 pci->iatu_unroll_enabled |= DWC_IATU_UNROLL_EN; in dw_pcie_setup()
568 if (!pci->atu_base) in dw_pcie_setup()
569 pci->atu_base = in dw_pcie_setup()
571 if (IS_ERR(pci->atu_base)) in dw_pcie_setup()
572 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; in dw_pcie_setup()
574 dev_dbg(pci->dev, "iATU unroll: %s\n", in dw_pcie_setup()
575 pci->iatu_unroll_enabled & DWC_IATU_UNROLL_EN ? in dw_pcie_setup()
578 if (pci->link_gen > 0) in dw_pcie_setup()
579 dw_pcie_link_set_max_speed(pci, pci->link_gen); in dw_pcie_setup()
582 if (pci->n_fts[0]) { in dw_pcie_setup()
583 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); in dw_pcie_setup()
585 val |= PORT_AFR_N_FTS(pci->n_fts[0]); in dw_pcie_setup()
586 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]); in dw_pcie_setup()
587 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); in dw_pcie_setup()
591 if (pci->n_fts[1]) { in dw_pcie_setup()
592 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); in dw_pcie_setup()
594 val |= pci->n_fts[pci->link_gen - 1]; in dw_pcie_setup()
595 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); in dw_pcie_setup()
598 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); in dw_pcie_setup()
601 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); in dw_pcie_setup()
604 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); in dw_pcie_setup()
607 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); in dw_pcie_setup()
610 of_property_read_u32(np, "num-lanes", &pci->num_lanes); in dw_pcie_setup()
611 if (!pci->num_lanes) { in dw_pcie_setup()
612 dev_dbg(pci->dev, "Using h/w default number of lanes\n"); in dw_pcie_setup()
619 switch (pci->num_lanes) { in dw_pcie_setup()
633 dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes); in dw_pcie_setup()
636 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); in dw_pcie_setup()
639 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); in dw_pcie_setup()
641 switch (pci->num_lanes) { in dw_pcie_setup()
655 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); in dw_pcie_setup()