Lines Matching refs:MESON_MX_EFUSE_CNTL1
22 #define MESON_MX_EFUSE_CNTL1 0x04 macro
72 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_hw_enable()
83 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_hw_disable()
98 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read_addr()
102 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read_addr()
105 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read_addr()
109 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read_addr()
112 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read_addr()
119 readl(efuse->base + MESON_MX_EFUSE_CNTL1); in meson_mx_efuse_read_addr()
121 err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read_addr()
147 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read()
162 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_read()