Lines Matching +full:0 +full:x0000fc00
20 IQK_ROUND_INVALID = 0xff,
37 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
53 u8 channel_plan; /* 0xb8 */
57 u8 pa_type; /* 0xbc */
58 u8 lna_type_2g[2]; /* 0xbd */
68 u8 rf_antenna_option; /* 0xc9 */
77 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
81 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
83 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
85 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
87 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
89 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
91 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
93 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
95 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
110 *ext = (t >> 7) & 0x1; /* Q.16 --> Q.9; get LSB of Q.9 */ in iqk_mult()
115 #define OFDM_SWING_A(swing) FIELD_GET(GENMASK(9, 0), swing)
123 #define IQK_TX_X_ERR 0x142
124 #define IQK_TX_Y_ERR 0x42
125 #define IQK_RX_X_UPPER 0x11a
126 #define IQK_RX_X_LOWER 0xe6
127 #define IQK_RX_Y_LMT 0x1a
128 #define IQK_TX_OK BIT(0)
132 #define SPUR_THRES 0x16
134 #define DIS_3WIRE 0xccf000c0
135 #define EN_3WIRE 0xccc000c0
136 #define START_PSD 0x400000
137 #define FREQ_CH13 0xfccd
138 #define FREQ_CH14 0xff9a
139 #define RFCFGCH_CHANNEL_MASK GENMASK(7, 0)
143 #define BIT_MASK_RFMOD BIT(0)
146 #define REG_GPIO_INTM 0x0048
147 #define REG_BTG_SEL 0x0067
149 #define REG_LTECOEX_PATH_CONTROL 0x0070
150 #define REG_LTECOEX_CTRL 0x07c0
151 #define REG_LTECOEX_WRITE_DATA 0x07c4
152 #define REG_LTECOEX_READ_DATA 0x07c8
153 #define REG_PSDFN 0x0808
154 #define REG_BB_PWR_SAV1_11N 0x0874
155 #define REG_ANA_PARAM1 0x0880
156 #define REG_ANALOG_P4 0x088c
157 #define REG_PSDRPT 0x08b4
158 #define REG_FPGA1_RFMOD 0x0900
159 #define REG_BB_SEL_BTG 0x0948
160 #define REG_BBRX_DFIR 0x0954
163 #define REG_CCK0_SYS 0x0a00
165 #define REG_CCK_ANT_SEL_11N 0x0a04
166 #define REG_CCK_FA_RST_11N 0x0a2c
173 #define REG_CCK_FA_LSB_11N 0x0a5c
174 #define REG_CCK_FA_MSB_11N 0x0a58
175 #define REG_CCK_CCA_CNT_11N 0x0a60
176 #define BIT_MASK_CCK_FA_MSB GENMASK(7, 0)
178 #define REG_OFDM_FA_HOLDC_11N 0x0c00
180 #define REG_BB_RX_PATH_11N 0x0c04
181 #define REG_TRMUX_11N 0x0c08
182 #define REG_OFDM_FA_RSTC_11N 0x0c0c
184 #define REG_A_RXIQI 0x0c14
185 #define BIT_MASK_RXIQ_S1_X 0x000003FF
186 #define BIT_MASK_RXIQ_S1_Y1 0x0000FC00
187 #define BIT_SET_RXIQ_S1_Y1(y) ((y) & 0x3F)
188 #define REG_OFDM0_RXDSP 0x0c40
191 #define REG_OFDM_0_ECCA_THRESHOLD 0x0c4c
196 #define REG_OFDM0_XAAGC1 0x0c50
197 #define REG_OFDM0_XBAGC1 0x0c58
198 #define REG_AGCRSSI 0x0c78
199 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0x0c80
200 #define BIT_MASK_TXIQ_ELM_A 0x03ff
201 #define BIT_SET_TXIQ_ELM_ACD(a, c, d) (((d) << 22) | (((c) & 0x3F) << 16) | \
202 ((a) & 0x03ff))
204 #define BIT_SET_TXIQ_ELM_C2(c) ((c) & 0x3F)
206 #define REG_TXIQK_MATRIXA_LSB2_11N 0x0c94
207 #define BIT_SET_TXIQ_ELM_C1(c) (((c) & 0x000003C0) >> 6)
208 #define REG_RXIQK_MATRIX_LSB_11N 0x0ca0
209 #define BIT_MASK_RXIQ_S1_Y2 0xF0000000
210 #define BIT_SET_RXIQ_S1_Y2(y) (((y) >> 6) & 0xF)
211 #define REG_TXIQ_AB_S0 0x0cd0
212 #define BIT_MASK_TXIQ_A_S0 0x000007FE
213 #define BIT_MASK_TXIQ_A_EXT_S0 BIT(0)
214 #define BIT_MASK_TXIQ_B_S0 0x0007E000
215 #define REG_TXIQ_CD_S0 0x0cd4
216 #define BIT_MASK_TXIQ_C_S0 0x000007FE
217 #define BIT_MASK_TXIQ_C_EXT_S0 BIT(0)
220 #define REG_RXIQ_AB_S0 0x0cd8
221 #define BIT_MASK_RXIQ_X_S0 0x000003FF
222 #define BIT_MASK_RXIQ_Y_S0 0x003FF000
223 #define REG_OFDM_FA_TYPE1_11N 0x0cf0
224 #define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0)
226 #define REG_OFDM_FA_RSTD_11N 0x0d00
229 #define REG_CTX 0x0d03
231 #define REG_OFDM1_CFOTRK 0x0d2c
233 #define REG_OFDM1_CSI1 0x0d40
234 #define REG_OFDM1_CSI2 0x0d44
235 #define REG_OFDM1_CSI3 0x0d48
236 #define REG_OFDM1_CSI4 0x0d4c
237 #define REG_OFDM_FA_TYPE2_11N 0x0da0
238 #define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0)
240 #define REG_OFDM_FA_TYPE3_11N 0x0da4
241 #define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0)
243 #define REG_OFDM_FA_TYPE4_11N 0x0da8
244 #define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0)
245 #define REG_FPGA0_IQK_11N 0x0e28
246 #define BIT_MASK_IQK_MOD 0xffffff00
247 #define EN_IQK 0x808000
248 #define RST_IQK 0x000000
249 #define REG_TXIQK_TONE_A_11N 0x0e30
250 #define REG_RXIQK_TONE_A_11N 0x0e34
251 #define REG_TXIQK_PI_A_11N 0x0e38
252 #define REG_RXIQK_PI_A_11N 0x0e3c
253 #define REG_TXIQK_11N 0x0e40
254 #define BIT_SET_TXIQK_11N(x, y) (0x80007C00 | ((x) << 16) | (y))
255 #define REG_RXIQK_11N 0x0e44
256 #define REG_IQK_AGC_PTS_11N 0x0e48
257 #define REG_IQK_AGC_RSP_11N 0x0e4c
258 #define REG_TX_IQK_TONE_B 0x0e50
259 #define REG_RX_IQK_TONE_B 0x0e54
260 #define REG_IQK_RES_TX 0x0e94
262 #define REG_IQK_RES_TY 0x0e9c
264 #define REG_IQK_RES_RX 0x0ea4
266 #define REG_IQK_RES_RY 0x0eac
271 #define REG_PAGE_F_RST_11N 0x0f14
273 #define REG_IGI_C_11N 0x0f84
274 #define REG_IGI_D_11N 0x0f88
275 #define REG_HT_CRC32_CNT_11N 0x0f90
276 #define BIT_MASK_HT_CRC_OK GENMASK(15, 0)
278 #define REG_OFDM_CRC32_CNT_11N 0x0f94
279 #define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0)
281 #define REG_HT_CRC32_CNT_11N_AGG 0x0fb8