Lines Matching refs:rtwdev
68 static void rtw8723d_lck(struct rtw_dev *rtwdev) in rtw8723d_lck() argument
74 val_ctx = rtw_read8(rtwdev, REG_CTX); in rtw8723d_lck()
76 rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE); in rtw8723d_lck()
78 rtw_write8(rtwdev, REG_TXPAUSE, 0xFF); in rtw8723d_lck()
79 lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); in rtw8723d_lck()
81 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal | BIT_LCK); in rtw8723d_lck()
85 rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK); in rtw8723d_lck()
87 rtw_warn(rtwdev, "failed to poll LCK status bit\n"); in rtw8723d_lck()
89 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal); in rtw8723d_lck()
91 rtw_write8(rtwdev, REG_CTX, val_ctx); in rtw8723d_lck()
93 rtw_write8(rtwdev, REG_TXPAUSE, 0x00); in rtw8723d_lck()
118 static void rtw8723d_pwrtrack_init(struct rtw_dev *rtwdev) in rtw8723d_pwrtrack_init() argument
120 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_pwrtrack_init()
125 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { in rtw8723d_pwrtrack_init()
131 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; in rtw8723d_pwrtrack_init()
136 static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev) in rtw8723d_phy_set_param() argument
142 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, in rtw8723d_phy_set_param()
144 rtw_write8_set(rtwdev, REG_RF_CTRL, in rtw8723d_phy_set_param()
146 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80); in rtw8723d_phy_set_param()
148 rtw_phy_load_tables(rtwdev); in rtw8723d_phy_set_param()
151 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF); in rtw8723d_phy_set_param()
152 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, BIT_HIQ_NO_LMT_EN_ROOT); in rtw8723d_phy_set_param()
153 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN); in rtw8723d_phy_set_param()
155 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8723d_phy_set_param()
156 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, in rtw8723d_phy_set_param()
158 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN); in rtw8723d_phy_set_param()
159 if ((rtwdev->efuse.afe >> 4) == 14) { in rtw8723d_phy_set_param()
160 rtw_write32_set(rtwdev, REG_AFE_CTRL3, BIT_XTAL_GMP_BIT4); in rtw8723d_phy_set_param()
161 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BITS_PLL); in rtw8723d_phy_set_param()
162 rtw_write32_set(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA1); in rtw8723d_phy_set_param()
163 rtw_write32_clr(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA0); in rtw8723d_phy_set_param()
166 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); in rtw8723d_phy_set_param()
167 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); in rtw8723d_phy_set_param()
168 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL); in rtw8723d_phy_set_param()
169 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL); in rtw8723d_phy_set_param()
170 rtw_write8(rtwdev, REG_ATIMWND, 0x2); in rtw8723d_phy_set_param()
171 rtw_write8(rtwdev, REG_BCN_CTRL, in rtw8723d_phy_set_param()
173 val32 = rtw_read32(rtwdev, REG_TBTT_PROHIBIT); in rtw8723d_phy_set_param()
176 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, val32); in rtw8723d_phy_set_param()
177 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL); in rtw8723d_phy_set_param()
178 rtw_write8(rtwdev, REG_AGGR_BREAK_TIME, WLAN_AGG_BRK_TIME); in rtw8723d_phy_set_param()
179 rtw_write16(rtwdev, REG_NAV_PROT_LEN, WLAN_NAV_PROT_LEN); in rtw8723d_phy_set_param()
180 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS); in rtw8723d_phy_set_param()
181 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); in rtw8723d_phy_set_param()
182 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); in rtw8723d_phy_set_param()
183 rtw_write8(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU); in rtw8723d_phy_set_param()
184 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT); in rtw8723d_phy_set_param()
185 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR); in rtw8723d_phy_set_param()
186 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME); in rtw8723d_phy_set_param()
187 rtw_write8(rtwdev, REG_LEDCFG2, WLAN_ANT_SEL); in rtw8723d_phy_set_param()
189 rtw_write32(rtwdev, REG_LTR_IDLE_LATENCY, WLAN_LTR_IDLE_LAT); in rtw8723d_phy_set_param()
190 rtw_write32(rtwdev, REG_LTR_ACTIVE_LATENCY, WLAN_LTR_ACT_LAT); in rtw8723d_phy_set_param()
191 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC, WLAN_LTR_CTRL1); in rtw8723d_phy_set_param()
192 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC + 4, WLAN_LTR_CTRL2); in rtw8723d_phy_set_param()
194 rtw_phy_init(rtwdev); in rtw8723d_phy_set_param()
196 rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN); in rtw8723d_phy_set_param()
198 rtw8723d_lck(rtwdev); in rtw8723d_phy_set_param()
200 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); in rtw8723d_phy_set_param()
201 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); in rtw8723d_phy_set_param()
203 rtw8723d_pwrtrack_init(rtwdev); in rtw8723d_phy_set_param()
212 static int rtw8723d_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) in rtw8723d_read_efuse() argument
214 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8723d_read_efuse()
237 switch (rtw_hci_type(rtwdev)) { in rtw8723d_read_efuse()
249 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, in query_phy_status_page0() argument
252 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page0()
264 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, in query_phy_status_page1() argument
267 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page1()
303 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, in query_phy_status() argument
312 query_phy_status_page0(rtwdev, phy_status, pkt_stat); in query_phy_status()
315 query_phy_status_page1(rtwdev, phy_status, pkt_stat); in query_phy_status()
318 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); in query_phy_status()
323 static void rtw8723d_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, in rtw8723d_query_rx_desc() argument
328 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; in rtw8723d_query_rx_desc()
358 query_phy_status(rtwdev, phy_status, pkt_stat); in rtw8723d_query_rx_desc()
361 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); in rtw8723d_query_rx_desc()
364 static bool rtw8723d_check_spur_ov_thres(struct rtw_dev *rtwdev, in rtw8723d_check_spur_ov_thres() argument
377 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE); in rtw8723d_check_spur_ov_thres()
378 rtw_write32(rtwdev, REG_PSDFN, freq); in rtw8723d_check_spur_ov_thres()
379 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq); in rtw8723d_check_spur_ov_thres()
382 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres) in rtw8723d_check_spur_ov_thres()
385 rtw_write32(rtwdev, REG_PSDFN, freq); in rtw8723d_check_spur_ov_thres()
386 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE); in rtw8723d_check_spur_ov_thres()
391 static void rtw8723d_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch) in rtw8723d_cfg_notch() argument
394 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); in rtw8723d_cfg_notch()
395 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); in rtw8723d_cfg_notch()
396 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); in rtw8723d_cfg_notch()
397 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); in rtw8723d_cfg_notch()
398 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); in rtw8723d_cfg_notch()
399 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); in rtw8723d_cfg_notch()
400 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); in rtw8723d_cfg_notch()
406 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); in rtw8723d_cfg_notch()
407 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); in rtw8723d_cfg_notch()
408 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000); in rtw8723d_cfg_notch()
409 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); in rtw8723d_cfg_notch()
410 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); in rtw8723d_cfg_notch()
411 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); in rtw8723d_cfg_notch()
412 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); in rtw8723d_cfg_notch()
415 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); in rtw8723d_cfg_notch()
416 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); in rtw8723d_cfg_notch()
417 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); in rtw8723d_cfg_notch()
418 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); in rtw8723d_cfg_notch()
419 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); in rtw8723d_cfg_notch()
420 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000); in rtw8723d_cfg_notch()
421 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); in rtw8723d_cfg_notch()
424 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); in rtw8723d_cfg_notch()
425 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); in rtw8723d_cfg_notch()
430 static void rtw8723d_spur_cal(struct rtw_dev *rtwdev, u8 channel) in rtw8723d_spur_cal() argument
435 rtw8723d_cfg_notch(rtwdev, channel, false); in rtw8723d_spur_cal()
439 notch = rtw8723d_check_spur_ov_thres(rtwdev, channel, SPUR_THRES); in rtw8723d_spur_cal()
440 rtw8723d_cfg_notch(rtwdev, channel, notch); in rtw8723d_spur_cal()
443 static void rtw8723d_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) in rtw8723d_set_channel_rf() argument
447 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); in rtw8723d_set_channel_rf()
448 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK); in rtw8723d_set_channel_rf()
467 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a); in rtw8723d_set_channel_rf()
468 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b); in rtw8723d_set_channel_rf()
470 rtw8723d_spur_cal(rtwdev, channel); in rtw8723d_set_channel_rf()
486 static void rtw8723d_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, in rtw8723d_set_channel_bb() argument
495 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val); in rtw8723d_set_channel_bb()
499 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0); in rtw8723d_set_channel_bb()
500 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0); in rtw8723d_set_channel_bb()
501 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 1); in rtw8723d_set_channel_bb()
502 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa); in rtw8723d_set_channel_bb()
505 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1); in rtw8723d_set_channel_bb()
506 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1); in rtw8723d_set_channel_bb()
507 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0); in rtw8723d_set_channel_bb()
508 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND, in rtw8723d_set_channel_bb()
516 static void rtw8723d_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, in rtw8723d_set_channel() argument
519 rtw8723d_set_channel_rf(rtwdev, channel, bw); in rtw8723d_set_channel()
520 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); in rtw8723d_set_channel()
521 rtw8723d_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); in rtw8723d_set_channel()
534 static int rtw8723d_mac_init(struct rtw_dev *rtwdev) in rtw8723d_mac_init() argument
536 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); in rtw8723d_mac_init()
537 rtw_write32(rtwdev, REG_TCR, BIT_TCR_CFG); in rtw8723d_mac_init()
539 rtw_write16(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); in rtw8723d_mac_init()
540 rtw_write16(rtwdev, REG_RXFLTMAP1, WLAN_RX_FILTER1); in rtw8723d_mac_init()
541 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); in rtw8723d_mac_init()
542 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); in rtw8723d_mac_init()
544 rtw_write32(rtwdev, REG_INT_MIG, 0); in rtw8723d_mac_init()
545 rtw_write32(rtwdev, REG_MCUTST_1, 0x0); in rtw8723d_mac_init()
547 rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA); in rtw8723d_mac_init()
548 rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0); in rtw8723d_mac_init()
553 static void rtw8723d_shutdown(struct rtw_dev *rtwdev) in rtw8723d_shutdown() argument
555 rtw_write16_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS); in rtw8723d_shutdown()
558 static void rtw8723d_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) in rtw8723d_cfg_ldo25() argument
562 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); in rtw8723d_cfg_ldo25()
569 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); in rtw8723d_cfg_ldo25()
573 rtw8723d_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) in rtw8723d_set_tx_power_index_by_rate() argument
575 struct rtw_hal *hal = &rtwdev->hal; in rtw8723d_set_tx_power_index_by_rate()
585 rtw_warn(rtwdev, "rate 0x%x isn't supported\n", rate); in rtw8723d_set_tx_power_index_by_rate()
590 rtw_warn(rtwdev, "rate 0x%x isn't defined\n", rate); in rtw8723d_set_tx_power_index_by_rate()
594 rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index); in rtw8723d_set_tx_power_index_by_rate()
598 static void rtw8723d_set_tx_power_index(struct rtw_dev *rtwdev) in rtw8723d_set_tx_power_index() argument
600 struct rtw_hal *hal = &rtwdev->hal; in rtw8723d_set_tx_power_index()
605 rtw8723d_set_tx_power_index_by_rate(rtwdev, path, rs); in rtw8723d_set_tx_power_index()
609 static void rtw8723d_efuse_grant(struct rtw_dev *rtwdev, bool on) in rtw8723d_efuse_grant() argument
612 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); in rtw8723d_efuse_grant()
614 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR); in rtw8723d_efuse_grant()
615 rtw_write16_set(rtwdev, REG_SYS_CLKR, BIT_LOADER_CLK_EN | BIT_ANA8M); in rtw8723d_efuse_grant()
617 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); in rtw8723d_efuse_grant()
621 static void rtw8723d_false_alarm_statistics(struct rtw_dev *rtwdev) in rtw8723d_false_alarm_statistics() argument
623 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_false_alarm_statistics()
630 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1); in rtw8723d_false_alarm_statistics()
631 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1); in rtw8723d_false_alarm_statistics()
632 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1); in rtw8723d_false_alarm_statistics()
633 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1); in rtw8723d_false_alarm_statistics()
635 cck_fa_cnt = rtw_read32_mask(rtwdev, REG_CCK_FA_LSB_11N, MASKBYTE0); in rtw8723d_false_alarm_statistics()
636 cck_fa_cnt += rtw_read32_mask(rtwdev, REG_CCK_FA_MSB_11N, MASKBYTE3) << 8; in rtw8723d_false_alarm_statistics()
638 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE1_11N); in rtw8723d_false_alarm_statistics()
641 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE2_11N); in rtw8723d_false_alarm_statistics()
644 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE3_11N); in rtw8723d_false_alarm_statistics()
647 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE4_11N); in rtw8723d_false_alarm_statistics()
654 dm_info->cck_err_cnt = rtw_read32(rtwdev, REG_IGI_C_11N); in rtw8723d_false_alarm_statistics()
655 dm_info->cck_ok_cnt = rtw_read32(rtwdev, REG_IGI_D_11N); in rtw8723d_false_alarm_statistics()
656 crc32_cnt = rtw_read32(rtwdev, REG_OFDM_CRC32_CNT_11N); in rtw8723d_false_alarm_statistics()
659 crc32_cnt = rtw_read32(rtwdev, REG_HT_CRC32_CNT_11N); in rtw8723d_false_alarm_statistics()
665 val32 = rtw_read32(rtwdev, REG_CCK_CCA_CNT_11N); in rtw8723d_false_alarm_statistics()
671 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1); in rtw8723d_false_alarm_statistics()
672 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0); in rtw8723d_false_alarm_statistics()
673 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1); in rtw8723d_false_alarm_statistics()
674 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0); in rtw8723d_false_alarm_statistics()
675 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0); in rtw8723d_false_alarm_statistics()
676 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0); in rtw8723d_false_alarm_statistics()
677 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0); in rtw8723d_false_alarm_statistics()
678 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2); in rtw8723d_false_alarm_statistics()
679 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0); in rtw8723d_false_alarm_statistics()
680 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2); in rtw8723d_false_alarm_statistics()
681 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1); in rtw8723d_false_alarm_statistics()
682 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0); in rtw8723d_false_alarm_statistics()
718 static void rtw8723d_iqk_backup_regs(struct rtw_dev *rtwdev, in rtw8723d_iqk_backup_regs() argument
724 backup->adda[i] = rtw_read32(rtwdev, iqk_adda_regs[i]); in rtw8723d_iqk_backup_regs()
727 backup->mac8[i] = rtw_read8(rtwdev, iqk_mac8_regs[i]); in rtw8723d_iqk_backup_regs()
729 backup->mac32[i] = rtw_read32(rtwdev, iqk_mac32_regs[i]); in rtw8723d_iqk_backup_regs()
732 backup->bb[i] = rtw_read32(rtwdev, iqk_bb_regs[i]); in rtw8723d_iqk_backup_regs()
734 backup->igia = rtw_read32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0); in rtw8723d_iqk_backup_regs()
735 backup->igib = rtw_read32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0); in rtw8723d_iqk_backup_regs()
737 backup->bb_sel_btg = rtw_read32(rtwdev, REG_BB_SEL_BTG); in rtw8723d_iqk_backup_regs()
740 static void rtw8723d_iqk_restore_regs(struct rtw_dev *rtwdev, in rtw8723d_iqk_restore_regs() argument
746 rtw_write32(rtwdev, iqk_adda_regs[i], backup->adda[i]); in rtw8723d_iqk_restore_regs()
749 rtw_write8(rtwdev, iqk_mac8_regs[i], backup->mac8[i]); in rtw8723d_iqk_restore_regs()
751 rtw_write32(rtwdev, iqk_mac32_regs[i], backup->mac32[i]); in rtw8723d_iqk_restore_regs()
754 rtw_write32(rtwdev, iqk_bb_regs[i], backup->bb[i]); in rtw8723d_iqk_restore_regs()
756 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); in rtw8723d_iqk_restore_regs()
757 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, backup->igia); in rtw8723d_iqk_restore_regs()
759 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50); in rtw8723d_iqk_restore_regs()
760 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, backup->igib); in rtw8723d_iqk_restore_regs()
762 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x01008c00); in rtw8723d_iqk_restore_regs()
763 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x01008c00); in rtw8723d_iqk_restore_regs()
766 static void rtw8723d_iqk_backup_path_ctrl(struct rtw_dev *rtwdev, in rtw8723d_iqk_backup_path_ctrl() argument
769 backup->btg_sel = rtw_read8(rtwdev, REG_BTG_SEL); in rtw8723d_iqk_backup_path_ctrl()
770 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] original 0x67 = 0x%x\n", in rtw8723d_iqk_backup_path_ctrl()
774 static void rtw8723d_iqk_config_path_ctrl(struct rtw_dev *rtwdev) in rtw8723d_iqk_config_path_ctrl() argument
776 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1); in rtw8723d_iqk_config_path_ctrl()
777 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] set 0x67 = 0x%x\n", in rtw8723d_iqk_config_path_ctrl()
778 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); in rtw8723d_iqk_config_path_ctrl()
781 static void rtw8723d_iqk_restore_path_ctrl(struct rtw_dev *rtwdev, in rtw8723d_iqk_restore_path_ctrl() argument
784 rtw_write8(rtwdev, REG_BTG_SEL, backup->btg_sel); in rtw8723d_iqk_restore_path_ctrl()
785 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] restore 0x67 = 0x%x\n", in rtw8723d_iqk_restore_path_ctrl()
786 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); in rtw8723d_iqk_restore_path_ctrl()
789 static void rtw8723d_iqk_backup_lte_path_gnt(struct rtw_dev *rtwdev, in rtw8723d_iqk_backup_lte_path_gnt() argument
792 backup->lte_path = rtw_read32(rtwdev, REG_LTECOEX_PATH_CONTROL); in rtw8723d_iqk_backup_lte_path_gnt()
793 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0038); in rtw8723d_iqk_backup_lte_path_gnt()
795 backup->lte_gnt = rtw_read32(rtwdev, REG_LTECOEX_READ_DATA); in rtw8723d_iqk_backup_lte_path_gnt()
796 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] OriginalGNT = 0x%x\n", in rtw8723d_iqk_backup_lte_path_gnt()
800 static void rtw8723d_iqk_config_lte_path_gnt(struct rtw_dev *rtwdev) in rtw8723d_iqk_config_lte_path_gnt() argument
802 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, 0x0000ff00); in rtw8723d_iqk_config_lte_path_gnt()
803 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc0020038); in rtw8723d_iqk_config_lte_path_gnt()
804 rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL, BIT_LTE_MUX_CTRL_PATH, 0x1); in rtw8723d_iqk_config_lte_path_gnt()
807 static void rtw8723d_iqk_restore_lte_path_gnt(struct rtw_dev *rtwdev, in rtw8723d_iqk_restore_lte_path_gnt() argument
810 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, bak->lte_gnt); in rtw8723d_iqk_restore_lte_path_gnt()
811 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc00f0038); in rtw8723d_iqk_restore_lte_path_gnt()
812 rtw_write32(rtwdev, REG_LTECOEX_PATH_CONTROL, bak->lte_path); in rtw8723d_iqk_restore_lte_path_gnt()
855 static u8 rtw8723d_iqk_check_tx_failed(struct rtw_dev *rtwdev, in rtw8723d_iqk_check_tx_failed() argument
861 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n", in rtw8723d_iqk_check_tx_failed()
862 rtw_read32(rtwdev, REG_IQK_RES_RY)); in rtw8723d_iqk_check_tx_failed()
863 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", in rtw8723d_iqk_check_tx_failed()
864 rtw_read32(rtwdev, REG_IQK_RES_TX), in rtw8723d_iqk_check_tx_failed()
865 rtw_read32(rtwdev, REG_IQK_RES_TY)); in rtw8723d_iqk_check_tx_failed()
866 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_iqk_check_tx_failed()
868 rtw_read32(rtwdev, 0xe90), in rtw8723d_iqk_check_tx_failed()
869 rtw_read32(rtwdev, 0xe98)); in rtw8723d_iqk_check_tx_failed()
871 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL); in rtw8723d_iqk_check_tx_failed()
872 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); in rtw8723d_iqk_check_tx_failed()
873 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); in rtw8723d_iqk_check_tx_failed()
878 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s TXIQK is failed\n", in rtw8723d_iqk_check_tx_failed()
884 static u8 rtw8723d_iqk_check_rx_failed(struct rtw_dev *rtwdev, in rtw8723d_iqk_check_rx_failed() argument
890 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n", in rtw8723d_iqk_check_rx_failed()
891 rtw_read32(rtwdev, REG_IQK_RES_RX), in rtw8723d_iqk_check_rx_failed()
892 rtw_read32(rtwdev, REG_IQK_RES_RY)); in rtw8723d_iqk_check_rx_failed()
894 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_iqk_check_rx_failed()
896 rtw_read32(rtwdev, 0xea0), in rtw8723d_iqk_check_rx_failed()
897 rtw_read32(rtwdev, 0xea8)); in rtw8723d_iqk_check_rx_failed()
899 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL); in rtw8723d_iqk_check_rx_failed()
900 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); in rtw8723d_iqk_check_rx_failed()
901 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); in rtw8723d_iqk_check_rx_failed()
908 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s RXIQK STEP2 is failed\n", in rtw8723d_iqk_check_rx_failed()
914 static void rtw8723d_iqk_one_shot(struct rtw_dev *rtwdev, bool tx, in rtw8723d_iqk_one_shot() argument
920 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); in rtw8723d_iqk_one_shot()
921 rtw8723d_iqk_config_lte_path_gnt(rtwdev); in rtw8723d_iqk_one_shot()
923 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0054); in rtw8723d_iqk_one_shot()
925 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] GNT_BT @%s %sIQK1 = 0x%x\n", in rtw8723d_iqk_one_shot()
927 rtw_read32(rtwdev, REG_LTECOEX_READ_DATA)); in rtw8723d_iqk_one_shot()
928 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x948 @%s %sIQK1 = 0x%x\n", in rtw8723d_iqk_one_shot()
930 rtw_read32(rtwdev, REG_BB_SEL_BTG)); in rtw8723d_iqk_one_shot()
933 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, pts); in rtw8723d_iqk_one_shot()
934 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000); in rtw8723d_iqk_one_shot()
936 if (!check_hw_ready(rtwdev, REG_IQK_RES_RY, BIT_IQK_DONE, 1)) in rtw8723d_iqk_one_shot()
937 rtw_warn(rtwdev, "%s %s IQK isn't done\n", iqk_cfg->name, in rtw8723d_iqk_one_shot()
941 static void rtw8723d_iqk_txrx_path_post(struct rtw_dev *rtwdev, in rtw8723d_iqk_txrx_path_post() argument
945 rtw8723d_iqk_restore_lte_path_gnt(rtwdev, backup); in rtw8723d_iqk_txrx_path_post()
946 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg); in rtw8723d_iqk_txrx_path_post()
949 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); in rtw8723d_iqk_txrx_path_post()
951 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x0); in rtw8723d_iqk_txrx_path_post()
952 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, BIT(0), 0x0); in rtw8723d_iqk_txrx_path_post()
953 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, BIT(0), 0x0); in rtw8723d_iqk_txrx_path_post()
956 static u8 rtw8723d_iqk_tx_path(struct rtw_dev *rtwdev, in rtw8723d_iqk_tx_path() argument
962 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s TXIQK!!\n", iqk_cfg->name); in rtw8723d_iqk_tx_path()
963 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s TXIQK = 0x%x\n", in rtw8723d_iqk_tx_path()
965 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); in rtw8723d_iqk_tx_path()
967 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg); in rtw8723d_iqk_tx_path()
968 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); in rtw8723d_iqk_tx_path()
970 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); in rtw8723d_iqk_tx_path()
971 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00004); in rtw8723d_iqk_tx_path()
972 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005d); in rtw8723d_iqk_tx_path()
973 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xBFFE0); in rtw8723d_iqk_tx_path()
974 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); in rtw8723d_iqk_tx_path()
977 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x08008c0c); in rtw8723d_iqk_tx_path()
978 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); in rtw8723d_iqk_tx_path()
979 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, iqk_cfg->val_txiqk_pi); in rtw8723d_iqk_tx_path()
980 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160200); in rtw8723d_iqk_tx_path()
981 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); in rtw8723d_iqk_tx_path()
982 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); in rtw8723d_iqk_tx_path()
985 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911); in rtw8723d_iqk_tx_path()
988 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); in rtw8723d_iqk_tx_path()
989 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); in rtw8723d_iqk_tx_path()
990 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x1E0, 0x3); in rtw8723d_iqk_tx_path()
991 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXIQGEN, 0x1F, 0xf); in rtw8723d_iqk_tx_path()
994 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x10, 0x1); in rtw8723d_iqk_tx_path()
995 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_bspad, 0x1, 0x1); in rtw8723d_iqk_tx_path()
997 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint); in rtw8723d_iqk_tx_path()
998 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel); in rtw8723d_iqk_tx_path()
1000 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s TXIQK = 0x%x\n", in rtw8723d_iqk_tx_path()
1002 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); in rtw8723d_iqk_tx_path()
1003 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s TXIQK = 0x%x\n", in rtw8723d_iqk_tx_path()
1005 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); in rtw8723d_iqk_tx_path()
1007 rtw8723d_iqk_one_shot(rtwdev, true, iqk_cfg); in rtw8723d_iqk_tx_path()
1008 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg); in rtw8723d_iqk_tx_path()
1010 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup); in rtw8723d_iqk_tx_path()
1015 static u8 rtw8723d_iqk_rx_path(struct rtw_dev *rtwdev, in rtw8723d_iqk_rx_path() argument
1022 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK Step1!!\n", in rtw8723d_iqk_rx_path()
1024 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK1 = 0x%x\n", in rtw8723d_iqk_rx_path()
1026 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); in rtw8723d_iqk_rx_path()
1027 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg); in rtw8723d_iqk_rx_path()
1029 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); in rtw8723d_iqk_rx_path()
1032 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); in rtw8723d_iqk_rx_path()
1033 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); in rtw8723d_iqk_rx_path()
1036 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); in rtw8723d_iqk_rx_path()
1037 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); in rtw8723d_iqk_rx_path()
1038 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); in rtw8723d_iqk_rx_path()
1039 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); in rtw8723d_iqk_rx_path()
1040 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82160000); in rtw8723d_iqk_rx_path()
1041 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160000); in rtw8723d_iqk_rx_path()
1044 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911); in rtw8723d_iqk_rx_path()
1047 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); in rtw8723d_iqk_rx_path()
1048 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00006); in rtw8723d_iqk_rx_path()
1049 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f); in rtw8723d_iqk_rx_path()
1050 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xa7ffb); in rtw8723d_iqk_rx_path()
1051 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); in rtw8723d_iqk_rx_path()
1054 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); in rtw8723d_iqk_rx_path()
1055 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); in rtw8723d_iqk_rx_path()
1056 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint); in rtw8723d_iqk_rx_path()
1057 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel); in rtw8723d_iqk_rx_path()
1059 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1@ path %s RXIQK1 = 0x%x\n", in rtw8723d_iqk_rx_path()
1061 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); in rtw8723d_iqk_rx_path()
1062 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2@ path %s RXIQK1 = 0x%x\n", in rtw8723d_iqk_rx_path()
1064 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); in rtw8723d_iqk_rx_path()
1066 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg); in rtw8723d_iqk_rx_path()
1067 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg); in rtw8723d_iqk_rx_path()
1073 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); in rtw8723d_iqk_rx_path()
1074 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); in rtw8723d_iqk_rx_path()
1076 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y)); in rtw8723d_iqk_rx_path()
1077 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n", in rtw8723d_iqk_rx_path()
1078 rtw_read32(rtwdev, REG_TXIQK_11N), in rtw8723d_iqk_rx_path()
1081 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK STEP2!!\n", in rtw8723d_iqk_rx_path()
1083 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK2 = 0x%x\n", in rtw8723d_iqk_rx_path()
1085 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); in rtw8723d_iqk_rx_path()
1087 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); in rtw8723d_iqk_rx_path()
1088 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c); in rtw8723d_iqk_rx_path()
1089 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c); in rtw8723d_iqk_rx_path()
1090 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); in rtw8723d_iqk_rx_path()
1091 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); in rtw8723d_iqk_rx_path()
1092 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82170000); in rtw8723d_iqk_rx_path()
1093 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28171400); in rtw8723d_iqk_rx_path()
1096 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1); in rtw8723d_iqk_rx_path()
1099 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); in rtw8723d_iqk_rx_path()
1101 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x80000, 0x1); in rtw8723d_iqk_rx_path()
1102 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00007); in rtw8723d_iqk_rx_path()
1103 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f); in rtw8723d_iqk_rx_path()
1104 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xb3fdb); in rtw8723d_iqk_rx_path()
1105 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); in rtw8723d_iqk_rx_path()
1107 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s RXIQK2 = 0x%x\n", in rtw8723d_iqk_rx_path()
1109 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); in rtw8723d_iqk_rx_path()
1110 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s RXIQK2 = 0x%x\n", in rtw8723d_iqk_rx_path()
1112 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); in rtw8723d_iqk_rx_path()
1114 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg); in rtw8723d_iqk_rx_path()
1115 status |= rtw8723d_iqk_check_rx_failed(rtwdev, iqk_cfg); in rtw8723d_iqk_rx_path()
1118 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup); in rtw8723d_iqk_rx_path()
1124 void rtw8723d_iqk_fill_s1_matrix(struct rtw_dev *rtwdev, const s32 result[]) in rtw8723d_iqk_fill_s1_matrix() argument
1134 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, in rtw8723d_iqk_fill_s1_matrix()
1139 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, in rtw8723d_iqk_fill_s1_matrix()
1141 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, in rtw8723d_iqk_fill_s1_matrix()
1146 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, in rtw8723d_iqk_fill_s1_matrix()
1148 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, in rtw8723d_iqk_fill_s1_matrix()
1150 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, in rtw8723d_iqk_fill_s1_matrix()
1153 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_iqk_fill_s1_matrix()
1156 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_iqk_fill_s1_matrix()
1162 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_X, in rtw8723d_iqk_fill_s1_matrix()
1164 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_Y1, in rtw8723d_iqk_fill_s1_matrix()
1166 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2, in rtw8723d_iqk_fill_s1_matrix()
1171 void rtw8723d_iqk_fill_s0_matrix(struct rtw_dev *rtwdev, const s32 result[]) in rtw8723d_iqk_fill_s0_matrix() argument
1181 oldval_0 = rtw_read32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0); in rtw8723d_iqk_fill_s0_matrix()
1186 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, tx0_a); in rtw8723d_iqk_fill_s0_matrix()
1187 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, tx0_a_ext); in rtw8723d_iqk_fill_s0_matrix()
1192 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, tx0_c); in rtw8723d_iqk_fill_s0_matrix()
1193 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, tx0_c_ext); in rtw8723d_iqk_fill_s0_matrix()
1198 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_X_S0, in rtw8723d_iqk_fill_s0_matrix()
1200 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_Y_S0, in rtw8723d_iqk_fill_s0_matrix()
1204 static void rtw8723d_iqk_path_adda_on(struct rtw_dev *rtwdev) in rtw8723d_iqk_path_adda_on() argument
1209 rtw_write32(rtwdev, iqk_adda_regs[i], 0x03c00016); in rtw8723d_iqk_path_adda_on()
1212 static void rtw8723d_iqk_config_mac(struct rtw_dev *rtwdev) in rtw8723d_iqk_config_mac() argument
1214 rtw_write8(rtwdev, REG_TXPAUSE, 0xff); in rtw8723d_iqk_config_mac()
1218 void rtw8723d_iqk_rf_standby(struct rtw_dev *rtwdev, enum rtw_rf_path path) in rtw8723d_iqk_rf_standby() argument
1220 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path-%s standby mode!\n", in rtw8723d_iqk_rf_standby()
1223 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); in rtw8723d_iqk_rf_standby()
1225 rtw_write_rf(rtwdev, path, RF_MODE, RFREG_MASK, 0x10000); in rtw8723d_iqk_rf_standby()
1226 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); in rtw8723d_iqk_rf_standby()
1230 bool rtw8723d_iqk_similarity_cmp(struct rtw_dev *rtwdev, s32 result[][IQK_NR], in rtw8723d_iqk_similarity_cmp() argument
1288 void rtw8723d_iqk_precfg_path(struct rtw_dev *rtwdev, enum rtw8723d_path path) in rtw8723d_iqk_precfg_path() argument
1291 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_A); in rtw8723d_iqk_precfg_path()
1292 rtw8723d_iqk_path_adda_on(rtwdev); in rtw8723d_iqk_precfg_path()
1295 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); in rtw8723d_iqk_precfg_path()
1296 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); in rtw8723d_iqk_precfg_path()
1297 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); in rtw8723d_iqk_precfg_path()
1300 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_B); in rtw8723d_iqk_precfg_path()
1301 rtw8723d_iqk_path_adda_on(rtwdev); in rtw8723d_iqk_precfg_path()
1306 void rtw8723d_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t, in rtw8723d_iqk_one_round() argument
1312 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_iqk_one_round()
1315 rtw8723d_iqk_path_adda_on(rtwdev); in rtw8723d_iqk_one_round()
1316 rtw8723d_iqk_config_mac(rtwdev); in rtw8723d_iqk_one_round()
1317 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf); in rtw8723d_iqk_one_round()
1318 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05611); in rtw8723d_iqk_one_round()
1319 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4); in rtw8723d_iqk_one_round()
1320 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204200); in rtw8723d_iqk_one_round()
1321 rtw8723d_iqk_precfg_path(rtwdev, PATH_S1); in rtw8723d_iqk_one_round()
1324 s1_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup); in rtw8723d_iqk_one_round()
1326 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_iqk_one_round()
1329 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); in rtw8723d_iqk_one_round()
1331 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); in rtw8723d_iqk_one_round()
1335 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Tx IQK Fail!!\n"); in rtw8723d_iqk_one_round()
1341 s1_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup); in rtw8723d_iqk_one_round()
1343 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_iqk_one_round()
1346 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); in rtw8723d_iqk_one_round()
1348 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); in rtw8723d_iqk_one_round()
1352 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Rx IQK Fail!!\n"); in rtw8723d_iqk_one_round()
1358 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 IQK is failed!!\n"); in rtw8723d_iqk_one_round()
1360 rtw8723d_iqk_precfg_path(rtwdev, PATH_S0); in rtw8723d_iqk_one_round()
1363 s0_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup); in rtw8723d_iqk_one_round()
1365 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_iqk_one_round()
1368 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); in rtw8723d_iqk_one_round()
1370 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); in rtw8723d_iqk_one_round()
1374 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Tx IQK Fail!!\n"); in rtw8723d_iqk_one_round()
1380 s0_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup); in rtw8723d_iqk_one_round()
1382 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_iqk_one_round()
1386 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); in rtw8723d_iqk_one_round()
1388 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); in rtw8723d_iqk_one_round()
1392 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Rx IQK Fail!!\n"); in rtw8723d_iqk_one_round()
1398 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 IQK is failed!!\n"); in rtw8723d_iqk_one_round()
1400 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); in rtw8723d_iqk_one_round()
1403 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_iqk_one_round()
1407 static void rtw8723d_phy_calibration(struct rtw_dev *rtwdev) in rtw8723d_phy_calibration() argument
1409 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_phy_calibration()
1416 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!!!\n"); in rtw8723d_phy_calibration()
1420 rtw8723d_iqk_backup_path_ctrl(rtwdev, &backup); in rtw8723d_phy_calibration()
1421 rtw8723d_iqk_backup_lte_path_gnt(rtwdev, &backup); in rtw8723d_phy_calibration()
1422 rtw8723d_iqk_backup_regs(rtwdev, &backup); in rtw8723d_phy_calibration()
1425 rtw8723d_iqk_config_path_ctrl(rtwdev); in rtw8723d_phy_calibration()
1426 rtw8723d_iqk_config_lte_path_gnt(rtwdev); in rtw8723d_phy_calibration()
1428 rtw8723d_iqk_one_round(rtwdev, result, i, &backup); in rtw8723d_phy_calibration()
1431 rtw8723d_iqk_restore_regs(rtwdev, &backup); in rtw8723d_phy_calibration()
1432 rtw8723d_iqk_restore_lte_path_gnt(rtwdev, &backup); in rtw8723d_phy_calibration()
1433 rtw8723d_iqk_restore_path_ctrl(rtwdev, &backup); in rtw8723d_phy_calibration()
1436 good = rtw8723d_iqk_similarity_cmp(rtwdev, result, j, i); in rtw8723d_phy_calibration()
1440 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_phy_calibration()
1463 rtw8723d_iqk_fill_s1_matrix(rtwdev, result[final_candidate]); in rtw8723d_phy_calibration()
1464 rtw8723d_iqk_fill_s0_matrix(rtwdev, result[final_candidate]); in rtw8723d_phy_calibration()
1473 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg); in rtw8723d_phy_calibration()
1475 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n", in rtw8723d_phy_calibration()
1479 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_phy_calibration()
1486 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_phy_calibration()
1488 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE), in rtw8723d_phy_calibration()
1489 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N), in rtw8723d_phy_calibration()
1490 rtw_read32(rtwdev, REG_A_RXIQI), in rtw8723d_phy_calibration()
1491 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N)); in rtw8723d_phy_calibration()
1492 rtw_dbg(rtwdev, RTW_DBG_RFK, in rtw8723d_phy_calibration()
1494 rtw_read32(rtwdev, REG_TXIQ_AB_S0), in rtw8723d_phy_calibration()
1495 rtw_read32(rtwdev, REG_TXIQ_CD_S0), in rtw8723d_phy_calibration()
1496 rtw_read32(rtwdev, REG_RXIQ_AB_S0)); in rtw8723d_phy_calibration()
1498 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] finished\n"); in rtw8723d_phy_calibration()
1502 static void rtw8723d_coex_cfg_init(struct rtw_dev *rtwdev) in rtw8723d_coex_cfg_init() argument
1505 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); in rtw8723d_coex_cfg_init()
1509 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05); in rtw8723d_coex_cfg_init()
1512 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); in rtw8723d_coex_cfg_init()
1515 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); in rtw8723d_coex_cfg_init()
1516 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3); in rtw8723d_coex_cfg_init()
1519 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); in rtw8723d_coex_cfg_init()
1522 static void rtw8723d_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) in rtw8723d_coex_cfg_gnt_fix() argument
1526 static void rtw8723d_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) in rtw8723d_coex_cfg_gnt_debug() argument
1528 rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0); in rtw8723d_coex_cfg_gnt_debug()
1529 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0); in rtw8723d_coex_cfg_gnt_debug()
1530 rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0); in rtw8723d_coex_cfg_gnt_debug()
1531 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0); in rtw8723d_coex_cfg_gnt_debug()
1532 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0); in rtw8723d_coex_cfg_gnt_debug()
1533 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0); in rtw8723d_coex_cfg_gnt_debug()
1534 rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0); in rtw8723d_coex_cfg_gnt_debug()
1535 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0); in rtw8723d_coex_cfg_gnt_debug()
1538 static void rtw8723d_coex_cfg_rfe_type(struct rtw_dev *rtwdev) in rtw8723d_coex_cfg_rfe_type() argument
1540 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8723d_coex_cfg_rfe_type()
1541 struct rtw_coex *coex = &rtwdev->coex; in rtw8723d_coex_cfg_rfe_type()
1545 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; in rtw8723d_coex_cfg_rfe_type()
1555 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x80); in rtw8723d_coex_cfg_rfe_type()
1557 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x200); in rtw8723d_coex_cfg_rfe_type()
1560 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x280); in rtw8723d_coex_cfg_rfe_type()
1562 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x0); in rtw8723d_coex_cfg_rfe_type()
1566 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); in rtw8723d_coex_cfg_rfe_type()
1567 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); in rtw8723d_coex_cfg_rfe_type()
1568 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); in rtw8723d_coex_cfg_rfe_type()
1571 static void rtw8723d_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) in rtw8723d_coex_cfg_wl_tx_power() argument
1573 struct rtw_coex *coex = &rtwdev->coex; in rtw8723d_coex_cfg_wl_tx_power()
1588 rtw_write8(rtwdev, REG_ANA_PARAM1 + 3, pwr); in rtw8723d_coex_cfg_wl_tx_power()
1591 static void rtw8723d_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) in rtw8723d_coex_cfg_wl_rx_gain() argument
1593 struct rtw_coex *coex = &rtwdev->coex; in rtw8723d_coex_cfg_wl_rx_gain()
1620 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_on[i]); in rtw8723d_coex_cfg_wl_rx_gain()
1623 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_off[i]); in rtw8723d_coex_cfg_wl_rx_gain()
1627 static u8 rtw8723d_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev) in rtw8723d_pwrtrack_get_limit_ofdm() argument
1629 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_pwrtrack_get_limit_ofdm()
1653 rtw_warn(rtwdev, "pwrtrack unhandled tx_rate 0x%x\n", tx_rate); in rtw8723d_pwrtrack_get_limit_ofdm()
1660 static void rtw8723d_set_iqk_matrix_by_result(struct rtw_dev *rtwdev, in rtw8723d_set_iqk_matrix_by_result() argument
1663 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_set_iqk_matrix_by_result()
1697 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32); in rtw8723d_set_iqk_matrix_by_result()
1699 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, in rtw8723d_set_iqk_matrix_by_result()
1701 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); in rtw8723d_set_iqk_matrix_by_result()
1704 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); in rtw8723d_set_iqk_matrix_by_result()
1709 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, ele_D); in rtw8723d_set_iqk_matrix_by_result()
1710 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, ele_C); in rtw8723d_set_iqk_matrix_by_result()
1711 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, ele_A); in rtw8723d_set_iqk_matrix_by_result()
1713 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, in rtw8723d_set_iqk_matrix_by_result()
1715 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, in rtw8723d_set_iqk_matrix_by_result()
1717 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, in rtw8723d_set_iqk_matrix_by_result()
1723 static void rtw8723d_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index, in rtw8723d_set_iqk_matrix() argument
1726 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_set_iqk_matrix()
1738 rtw8723d_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path); in rtw8723d_set_iqk_matrix()
1745 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing); in rtw8723d_set_iqk_matrix()
1746 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, in rtw8723d_set_iqk_matrix()
1748 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); in rtw8723d_set_iqk_matrix()
1750 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); in rtw8723d_set_iqk_matrix()
1755 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, in rtw8723d_set_iqk_matrix()
1757 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_B_S0, in rtw8723d_set_iqk_matrix()
1759 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, in rtw8723d_set_iqk_matrix()
1761 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, in rtw8723d_set_iqk_matrix()
1763 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0); in rtw8723d_set_iqk_matrix()
1764 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0); in rtw8723d_set_iqk_matrix()
1765 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0); in rtw8723d_set_iqk_matrix()
1770 static void rtw8723d_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx, in rtw8723d_pwrtrack_set_ofdm_pwr() argument
1773 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_pwrtrack_set_ofdm_pwr()
1777 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A); in rtw8723d_pwrtrack_set_ofdm_pwr()
1778 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_B); in rtw8723d_pwrtrack_set_ofdm_pwr()
1781 static void rtw8723d_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx, in rtw8723d_pwrtrack_set_cck_pwr() argument
1784 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_pwrtrack_set_cck_pwr()
1788 rtw_write32_mask(rtwdev, 0xab4, 0x000007FF, in rtw8723d_pwrtrack_set_cck_pwr()
1792 static void rtw8723d_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) in rtw8723d_pwrtrack_set() argument
1794 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_pwrtrack_set()
1795 struct rtw_hal *hal = &rtwdev->hal; in rtw8723d_pwrtrack_set()
1801 limit_ofdm = rtw8723d_pwrtrack_get_limit_ofdm(rtwdev); in rtw8723d_pwrtrack_set()
1809 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm, in rtw8723d_pwrtrack_set()
1812 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, 0, in rtw8723d_pwrtrack_set()
1815 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0); in rtw8723d_pwrtrack_set()
1818 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, limit_cck, in rtw8723d_pwrtrack_set()
1821 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, 0, in rtw8723d_pwrtrack_set()
1824 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0); in rtw8723d_pwrtrack_set()
1826 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel); in rtw8723d_pwrtrack_set()
1829 static void rtw8723d_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path, in rtw8723d_pwrtrack_set_xtal() argument
1832 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_pwrtrack_set_xtal()
1833 const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl; in rtw8723d_pwrtrack_set_xtal()
1838 rtwdev->efuse.thermal_meter[therm_path]) in rtw8723d_pwrtrack_set_xtal()
1843 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8723d_pwrtrack_set_xtal()
1845 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, in rtw8723d_pwrtrack_set_xtal()
1849 static void rtw8723d_phy_pwrtrack(struct rtw_dev *rtwdev) in rtw8723d_phy_pwrtrack() argument
1851 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_phy_pwrtrack()
1856 rtw_phy_config_swing_table(rtwdev, &swing_table); in rtw8723d_phy_pwrtrack()
1858 if (rtwdev->efuse.thermal_meter[0] == 0xff) in rtw8723d_phy_pwrtrack()
1861 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); in rtw8723d_phy_pwrtrack()
1863 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); in rtw8723d_phy_pwrtrack()
1865 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev); in rtw8723d_phy_pwrtrack()
1868 rtw8723d_lck(rtwdev); in rtw8723d_phy_pwrtrack()
1872 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, in rtw8723d_phy_pwrtrack()
1876 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); in rtw8723d_phy_pwrtrack()
1880 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8723d_phy_pwrtrack()
1884 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, in rtw8723d_phy_pwrtrack()
1890 rtw8723d_pwrtrack_set(rtwdev, path); in rtw8723d_phy_pwrtrack()
1893 rtw8723d_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta); in rtw8723d_phy_pwrtrack()
1897 rtw8723d_phy_calibration(rtwdev); in rtw8723d_phy_pwrtrack()
1900 static void rtw8723d_pwr_track(struct rtw_dev *rtwdev) in rtw8723d_pwr_track() argument
1902 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8723d_pwr_track()
1903 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_pwr_track()
1909 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, in rtw8723d_pwr_track()
1915 rtw8723d_phy_pwrtrack(rtwdev); in rtw8723d_pwr_track()