Lines Matching +full:0 +full:x00020002
57 reg = 0; in rt2500pci_bbp_write()
82 * doesn't become available in time, reg will be 0xffffffff in rt2500pci_bbp_read()
83 * which means we return 0xff to the caller. in rt2500pci_bbp_read()
86 reg = 0; in rt2500pci_bbp_read()
89 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); in rt2500pci_bbp_read()
115 reg = 0; in rt2500pci_rf_write()
118 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); in rt2500pci_rf_write()
146 u32 reg = 0; in rt2500pci_eepromregister_write()
233 return 0; in rt2500pci_blink_set()
277 rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0); in rt2500pci_config_filter()
325 * When short preamble is enabled, we should set bit 0x08 in rt2500pci_config_erp()
331 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x162); in rt2500pci_config_erp()
332 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0xa2); in rt2500pci_config_erp()
338 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); in rt2500pci_config_erp()
339 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); in rt2500pci_config_erp()
345 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); in rt2500pci_config_erp()
346 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); in rt2500pci_config_erp()
352 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); in rt2500pci_config_erp()
353 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); in rt2500pci_config_erp()
359 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); in rt2500pci_config_erp()
360 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); in rt2500pci_config_erp()
419 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0); in rt2500pci_config_ant()
420 rt2x00_set_field32(®, BBPCSR1_CCK, 0); in rt2500pci_config_ant()
421 rt2x00_set_field32(®, BBPCSR1_OFDM, 0); in rt2500pci_config_ant()
436 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0); in rt2500pci_config_ant()
456 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0); in rt2500pci_config_ant()
458 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0); in rt2500pci_config_ant()
459 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0); in rt2500pci_config_ant()
490 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a, in rt2500pci_config_channel()
491 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a, in rt2500pci_config_channel()
492 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a, in rt2500pci_config_channel()
493 0x00080d2e, 0x00080d3a in rt2500pci_config_channel()
512 r70 = 0x46; in rt2500pci_config_channel()
523 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0); in rt2500pci_config_channel()
527 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0); in rt2500pci_config_channel()
575 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2500pci_config_ps()
582 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2500pci_config_ps()
640 rt2500pci_set_vgc(rt2x00dev, qual, 0x48); in rt2500pci_reset_tuner()
671 if (qual->vgc_level_reg >= 0x41) in rt2500pci_link_tuner()
680 rt2500pci_set_vgc(rt2x00dev, qual, 0x50); in rt2500pci_link_tuner()
688 rt2500pci_set_vgc(rt2x00dev, qual, 0x41); in rt2500pci_link_tuner()
696 if (qual->vgc_level_reg >= 0x41) { in rt2500pci_link_tuner()
707 if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) in rt2500pci_link_tuner()
709 else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) in rt2500pci_link_tuner()
724 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); in rt2500pci_start_queue()
785 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2500pci_stop_queue()
786 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2500pci_stop_queue()
787 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2500pci_stop_queue()
809 word = rt2x00_desc_read(entry_priv->desc, 0); in rt2500pci_get_entry_state()
813 word = rt2x00_desc_read(entry_priv->desc, 0); in rt2500pci_get_entry_state()
831 word = rt2x00_desc_read(entry_priv->desc, 0); in rt2500pci_clear_entry()
833 rt2x00_desc_write(entry_priv->desc, 0, word); in rt2500pci_clear_entry()
835 word = rt2x00_desc_read(entry_priv->desc, 0); in rt2500pci_clear_entry()
836 rt2x00_set_field32(&word, TXD_W0_VALID, 0); in rt2500pci_clear_entry()
837 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); in rt2500pci_clear_entry()
838 rt2x00_desc_write(entry_priv->desc, 0, word); in rt2500pci_clear_entry()
851 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); in rt2500pci_init_queues()
854 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); in rt2500pci_init_queues()
857 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; in rt2500pci_init_queues()
863 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; in rt2500pci_init_queues()
869 entry_priv = rt2x00dev->atim->entries[0].priv_data; in rt2500pci_init_queues()
875 entry_priv = rt2x00dev->bcn->entries[0].priv_data; in rt2500pci_init_queues()
886 entry_priv = rt2x00dev->rx->entries[0].priv_data; in rt2500pci_init_queues()
892 return 0; in rt2500pci_init_queues()
899 rt2x00mmio_register_write(rt2x00dev, PSCSR0, 0x00020002); in rt2500pci_init_registers()
900 rt2x00mmio_register_write(rt2x00dev, PSCSR1, 0x00000002); in rt2500pci_init_registers()
901 rt2x00mmio_register_write(rt2x00dev, PSCSR2, 0x00020002); in rt2500pci_init_registers()
902 rt2x00mmio_register_write(rt2x00dev, PSCSR3, 0x00000002); in rt2500pci_init_registers()
907 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); in rt2500pci_init_registers()
919 rt2x00_set_field32(®, CSR11_CW_SELECT, 0); in rt2500pci_init_registers()
923 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2500pci_init_registers()
924 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); in rt2500pci_init_registers()
925 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2500pci_init_registers()
926 rt2x00_set_field32(®, CSR14_TCFP, 0); in rt2500pci_init_registers()
927 rt2x00_set_field32(®, CSR14_TATIMW, 0); in rt2500pci_init_registers()
928 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2500pci_init_registers()
929 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); in rt2500pci_init_registers()
930 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); in rt2500pci_init_registers()
933 rt2x00mmio_register_write(rt2x00dev, CNT3, 0); in rt2500pci_init_registers()
979 rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0); in rt2500pci_init_registers()
980 rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0); in rt2500pci_init_registers()
988 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); in rt2500pci_init_registers()
990 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, 0x0000ff00); in rt2500pci_init_registers()
991 rt2x00mmio_register_write(rt2x00dev, TESTCSR, 0x000000f0); in rt2500pci_init_registers()
996 rt2x00mmio_register_write(rt2x00dev, MACCSR0, 0x00213223); in rt2500pci_init_registers()
997 rt2x00mmio_register_write(rt2x00dev, MACCSR1, 0x00235518); in rt2500pci_init_registers()
1007 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); in rt2500pci_init_registers()
1012 rt2x00mmio_register_write(rt2x00dev, BBPCSR1, 0x82188200); in rt2500pci_init_registers()
1014 rt2x00mmio_register_write(rt2x00dev, TXACKCSR0, 0x00000020); in rt2500pci_init_registers()
1018 rt2x00_set_field32(®, CSR1_BBP_RESET, 0); in rt2500pci_init_registers()
1019 rt2x00_set_field32(®, CSR1_HOST_READY, 0); in rt2500pci_init_registers()
1023 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); in rt2500pci_init_registers()
1035 return 0; in rt2500pci_init_registers()
1043 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { in rt2500pci_wait_bbp_ready()
1044 value = rt2500pci_bbp_read(rt2x00dev, 0); in rt2500pci_wait_bbp_ready()
1045 if ((value != 0xff) && (value != 0x00)) in rt2500pci_wait_bbp_ready()
1046 return 0; in rt2500pci_wait_bbp_ready()
1064 rt2500pci_bbp_write(rt2x00dev, 3, 0x02); in rt2500pci_init_bbp()
1065 rt2500pci_bbp_write(rt2x00dev, 4, 0x19); in rt2500pci_init_bbp()
1066 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c); in rt2500pci_init_bbp()
1067 rt2500pci_bbp_write(rt2x00dev, 15, 0x30); in rt2500pci_init_bbp()
1068 rt2500pci_bbp_write(rt2x00dev, 16, 0xac); in rt2500pci_init_bbp()
1069 rt2500pci_bbp_write(rt2x00dev, 18, 0x18); in rt2500pci_init_bbp()
1070 rt2500pci_bbp_write(rt2x00dev, 19, 0xff); in rt2500pci_init_bbp()
1071 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e); in rt2500pci_init_bbp()
1072 rt2500pci_bbp_write(rt2x00dev, 21, 0x08); in rt2500pci_init_bbp()
1073 rt2500pci_bbp_write(rt2x00dev, 22, 0x08); in rt2500pci_init_bbp()
1074 rt2500pci_bbp_write(rt2x00dev, 23, 0x08); in rt2500pci_init_bbp()
1075 rt2500pci_bbp_write(rt2x00dev, 24, 0x70); in rt2500pci_init_bbp()
1076 rt2500pci_bbp_write(rt2x00dev, 25, 0x40); in rt2500pci_init_bbp()
1077 rt2500pci_bbp_write(rt2x00dev, 26, 0x08); in rt2500pci_init_bbp()
1078 rt2500pci_bbp_write(rt2x00dev, 27, 0x23); in rt2500pci_init_bbp()
1079 rt2500pci_bbp_write(rt2x00dev, 30, 0x10); in rt2500pci_init_bbp()
1080 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b); in rt2500pci_init_bbp()
1081 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9); in rt2500pci_init_bbp()
1082 rt2500pci_bbp_write(rt2x00dev, 34, 0x12); in rt2500pci_init_bbp()
1083 rt2500pci_bbp_write(rt2x00dev, 35, 0x50); in rt2500pci_init_bbp()
1084 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4); in rt2500pci_init_bbp()
1085 rt2500pci_bbp_write(rt2x00dev, 40, 0x02); in rt2500pci_init_bbp()
1086 rt2500pci_bbp_write(rt2x00dev, 41, 0x60); in rt2500pci_init_bbp()
1087 rt2500pci_bbp_write(rt2x00dev, 53, 0x10); in rt2500pci_init_bbp()
1088 rt2500pci_bbp_write(rt2x00dev, 54, 0x18); in rt2500pci_init_bbp()
1089 rt2500pci_bbp_write(rt2x00dev, 56, 0x08); in rt2500pci_init_bbp()
1090 rt2500pci_bbp_write(rt2x00dev, 57, 0x10); in rt2500pci_init_bbp()
1091 rt2500pci_bbp_write(rt2x00dev, 58, 0x08); in rt2500pci_init_bbp()
1092 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d); in rt2500pci_init_bbp()
1093 rt2500pci_bbp_write(rt2x00dev, 62, 0x10); in rt2500pci_init_bbp()
1095 for (i = 0; i < EEPROM_BBP_SIZE; i++) { in rt2500pci_init_bbp()
1098 if (eeprom != 0xffff && eeprom != 0x0000) { in rt2500pci_init_bbp()
1105 return 0; in rt2500pci_init_bbp()
1163 return 0; in rt2500pci_enable_radio()
1171 rt2x00mmio_register_write(rt2x00dev, PWRCSR0, 0); in rt2500pci_disable_radio()
1197 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { in rt2500pci_set_state()
1202 return 0; in rt2500pci_set_state()
1213 int retval = 0; in rt2500pci_set_device_state()
1284 * Writing TXD word 0 must the last to prevent a race condition with in rt2500pci_write_tx_desc()
1288 word = rt2x00_desc_read(txd, 0); in rt2500pci_write_tx_desc()
1305 rt2x00_desc_write(txd, 0, word); in rt2500pci_write_tx_desc()
1328 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2500pci_write_beacon()
1363 word0 = rt2x00_desc_read(entry_priv->desc, 0); in rt2500pci_fill_rxdone()
1405 word = rt2x00_desc_read(entry_priv->desc, 0); in rt2500pci_txdone()
1414 txdesc.flags = 0; in rt2500pci_txdone()
1416 case 0: /* Success */ in rt2500pci_txdone()
1444 rt2x00_set_field32(®, irq_field, 0); in rt2500pci_enable_interrupt()
1470 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); in rt2500pci_txstatus_tasklet()
1471 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); in rt2500pci_txstatus_tasklet()
1472 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); in rt2500pci_txstatus_tasklet()
1570 eeprom.reg_data_in = 0; in rt2500pci_validate_eeprom()
1571 eeprom.reg_data_out = 0; in rt2500pci_validate_eeprom()
1572 eeprom.reg_data_clock = 0; in rt2500pci_validate_eeprom()
1573 eeprom.reg_chip_select = 0; in rt2500pci_validate_eeprom()
1585 if (word == 0xffff) { in rt2500pci_validate_eeprom()
1593 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); in rt2500pci_validate_eeprom()
1594 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); in rt2500pci_validate_eeprom()
1597 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); in rt2500pci_validate_eeprom()
1601 if (word == 0xffff) { in rt2500pci_validate_eeprom()
1602 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); in rt2500pci_validate_eeprom()
1603 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0); in rt2500pci_validate_eeprom()
1604 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0); in rt2500pci_validate_eeprom()
1606 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); in rt2500pci_validate_eeprom()
1610 if (word == 0xffff) { in rt2500pci_validate_eeprom()
1614 rt2x00_eeprom_dbg(rt2x00dev, "Calibrate offset: 0x%04x\n", in rt2500pci_validate_eeprom()
1618 return 0; in rt2500pci_validate_eeprom()
1697 return 0; in rt2500pci_init_eeprom()
1705 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1706 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1707 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1708 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1709 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1710 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1711 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1712 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1713 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1714 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1715 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1716 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1717 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1718 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1726 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1727 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1728 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1729 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1730 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1731 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1732 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1733 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1734 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1735 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1736 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1737 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1738 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1739 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1747 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1748 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1749 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1750 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1751 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1752 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1753 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1754 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1755 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1756 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1757 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1758 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1759 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1760 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1768 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1769 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1770 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1771 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1772 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1773 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1774 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1775 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1776 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1777 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1778 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1779 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1780 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1781 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1789 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1790 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1791 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1792 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1793 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1794 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1795 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1796 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1797 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1798 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1799 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1800 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1801 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1802 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1810 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1811 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1812 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1813 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1814 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1815 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1816 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1817 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1818 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1819 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1820 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1821 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1822 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1823 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1826 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1827 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1828 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1829 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1830 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1831 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1832 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1833 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1836 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1837 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1838 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1839 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1840 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1841 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1842 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1843 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1844 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1845 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1848 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1849 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1850 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1851 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1852 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1917 for (i = 0; i < 14; i++) { in rt2500pci_probe_hw_mode()
1929 return 0; in rt2500pci_probe_hw_mode()
1975 return 0; in rt2500pci_probe_hw()
2115 { PCI_DEVICE(0x1814, 0x0201) },
2116 { 0, }