Lines Matching refs:ah
97 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
201 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) in ath5k_extend_tsf() argument
203 u64 tsf = ath5k_hw_get_tsf64(ah); in ath5k_extend_tsf()
234 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; in ath5k_ioread32() local
235 return ath5k_hw_reg_read(ah, reg_offset); in ath5k_ioread32()
240 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; in ath5k_iowrite32() local
241 ath5k_hw_reg_write(ah, val, reg_offset); in ath5k_iowrite32()
257 struct ath5k_hw *ah = hw->priv; in ath5k_reg_notifier() local
258 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); in ath5k_reg_notifier()
296 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, in ath5k_setup_channels() argument
314 ATH5K_WARN(ah, "bad mode, not copying channels\n"); in ath5k_setup_channels()
331 if (!ath5k_channel_ok(ah, &channels[count])) in ath5k_setup_channels()
344 ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b) in ath5k_setup_rate_idx() argument
349 ah->rate_idx[b->band][i] = -1; in ath5k_setup_rate_idx()
352 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i; in ath5k_setup_rate_idx()
354 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; in ath5k_setup_rate_idx()
361 struct ath5k_hw *ah = hw->priv; in ath5k_setup_bands() local
366 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < NUM_NL80211_BANDS); in ath5k_setup_bands()
367 max_c = ARRAY_SIZE(ah->channels); in ath5k_setup_bands()
370 sband = &ah->sbands[NL80211_BAND_2GHZ]; in ath5k_setup_bands()
372 sband->bitrates = &ah->rates[NL80211_BAND_2GHZ][0]; in ath5k_setup_bands()
374 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) { in ath5k_setup_bands()
380 sband->channels = ah->channels; in ath5k_setup_bands()
381 sband->n_channels = ath5k_setup_channels(ah, sband->channels, in ath5k_setup_bands()
387 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) { in ath5k_setup_bands()
397 if (ah->ah_version == AR5K_AR5211) { in ath5k_setup_bands()
406 sband->channels = ah->channels; in ath5k_setup_bands()
407 sband->n_channels = ath5k_setup_channels(ah, sband->channels, in ath5k_setup_bands()
414 ath5k_setup_rate_idx(ah, sband); in ath5k_setup_bands()
417 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) { in ath5k_setup_bands()
418 sband = &ah->sbands[NL80211_BAND_5GHZ]; in ath5k_setup_bands()
420 sband->bitrates = &ah->rates[NL80211_BAND_5GHZ][0]; in ath5k_setup_bands()
426 sband->channels = &ah->channels[count_c]; in ath5k_setup_bands()
427 sband->n_channels = ath5k_setup_channels(ah, sband->channels, in ath5k_setup_bands()
432 ath5k_setup_rate_idx(ah, sband); in ath5k_setup_bands()
434 ath5k_debug_dump_bands(ah); in ath5k_setup_bands()
447 ath5k_chan_set(struct ath5k_hw *ah, struct cfg80211_chan_def *chandef) in ath5k_chan_set() argument
449 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_chan_set()
451 ah->curchan->center_freq, chandef->chan->center_freq); in ath5k_chan_set()
456 ah->ah_bwmode = AR5K_BWMODE_DEFAULT; in ath5k_chan_set()
459 ah->ah_bwmode = AR5K_BWMODE_5MHZ; in ath5k_chan_set()
462 ah->ah_bwmode = AR5K_BWMODE_10MHZ; in ath5k_chan_set()
475 return ath5k_reset(ah, chandef->chan, true); in ath5k_chan_set()
519 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah, in ath5k_update_bssid_mask_and_opmode() argument
522 struct ath_common *common = ath5k_hw_common(ah); in ath5k_update_bssid_mask_and_opmode()
542 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, in ath5k_update_bssid_mask_and_opmode()
544 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN); in ath5k_update_bssid_mask_and_opmode()
546 ah->opmode = iter_data.opmode; in ath5k_update_bssid_mask_and_opmode()
547 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED) in ath5k_update_bssid_mask_and_opmode()
549 ah->opmode = NL80211_IFTYPE_STATION; in ath5k_update_bssid_mask_and_opmode()
551 ath5k_hw_set_opmode(ah, ah->opmode); in ath5k_update_bssid_mask_and_opmode()
552 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", in ath5k_update_bssid_mask_and_opmode()
553 ah->opmode, ath_opmode_to_string(ah->opmode)); in ath5k_update_bssid_mask_and_opmode()
556 ath5k_hw_set_lladdr(ah, iter_data.active_mac); in ath5k_update_bssid_mask_and_opmode()
558 if (ath5k_hw_hasbssidmask(ah)) in ath5k_update_bssid_mask_and_opmode()
559 ath5k_hw_set_bssid_mask(ah, ah->bssidmask); in ath5k_update_bssid_mask_and_opmode()
567 ah->filter_flags |= AR5K_RX_FILTER_PROM; in ath5k_update_bssid_mask_and_opmode()
570 rfilt = ah->filter_flags; in ath5k_update_bssid_mask_and_opmode()
571 ath5k_hw_set_rx_filter(ah, rfilt); in ath5k_update_bssid_mask_and_opmode()
572 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); in ath5k_update_bssid_mask_and_opmode()
576 ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix) in ath5k_hw_to_driver_rix() argument
585 rix = ah->rate_idx[ah->curchan->band][hw_rix]; in ath5k_hw_to_driver_rix()
597 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr) in ath5k_rx_skb_alloc() argument
599 struct ath_common *common = ath5k_hw_common(ah); in ath5k_rx_skb_alloc()
611 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n", in ath5k_rx_skb_alloc()
616 *skb_addr = dma_map_single(ah->dev, in ath5k_rx_skb_alloc()
620 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) { in ath5k_rx_skb_alloc()
621 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__); in ath5k_rx_skb_alloc()
629 ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) in ath5k_rxbuf_setup() argument
636 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr); in ath5k_rxbuf_setup()
660 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); in ath5k_rxbuf_setup()
662 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__); in ath5k_rxbuf_setup()
666 if (ah->rxlink != NULL) in ath5k_rxbuf_setup()
667 *ah->rxlink = bf->daddr; in ath5k_rxbuf_setup()
668 ah->rxlink = &ds->ds_link; in ath5k_rxbuf_setup()
732 ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf, in ath5k_txbuf_setup() argument
751 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, in ath5k_txbuf_setup()
754 if (dma_mapping_error(ah->dev, bf->skbaddr)) in ath5k_txbuf_setup()
760 rate = ath5k_get_rate(ah->hw, info, bf, 0); in ath5k_txbuf_setup()
772 hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0); in ath5k_txbuf_setup()
785 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; in ath5k_txbuf_setup()
786 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw, in ath5k_txbuf_setup()
791 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; in ath5k_txbuf_setup()
792 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw, in ath5k_txbuf_setup()
796 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, in ath5k_txbuf_setup()
799 (ah->ah_txpower.txp_requested * 2), in ath5k_txbuf_setup()
801 bf->rates[0].count, keyidx, ah->ah_tx_ant, flags, in ath5k_txbuf_setup()
807 if (ah->ah_capabilities.cap_has_mrr_support) { in ath5k_txbuf_setup()
813 rate = ath5k_get_rate(ah->hw, info, bf, i); in ath5k_txbuf_setup()
817 mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i); in ath5k_txbuf_setup()
821 ath5k_hw_setup_mrr_tx_desc(ah, ds, in ath5k_txbuf_setup()
834 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); in ath5k_txbuf_setup()
839 ath5k_hw_start_tx_dma(ah, txq->qnum); in ath5k_txbuf_setup()
844 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); in ath5k_txbuf_setup()
853 ath5k_desc_alloc(struct ath5k_hw *ah) in ath5k_desc_alloc() argument
862 ah->desc_len = sizeof(struct ath5k_desc) * in ath5k_desc_alloc()
865 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len, in ath5k_desc_alloc()
866 &ah->desc_daddr, GFP_KERNEL); in ath5k_desc_alloc()
867 if (ah->desc == NULL) { in ath5k_desc_alloc()
868 ATH5K_ERR(ah, "can't allocate descriptors\n"); in ath5k_desc_alloc()
872 ds = ah->desc; in ath5k_desc_alloc()
873 da = ah->desc_daddr; in ath5k_desc_alloc()
874 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", in ath5k_desc_alloc()
875 ds, ah->desc_len, (unsigned long long)ah->desc_daddr); in ath5k_desc_alloc()
880 ATH5K_ERR(ah, "can't allocate bufptr\n"); in ath5k_desc_alloc()
884 ah->bufptr = bf; in ath5k_desc_alloc()
886 INIT_LIST_HEAD(&ah->rxbuf); in ath5k_desc_alloc()
890 list_add_tail(&bf->list, &ah->rxbuf); in ath5k_desc_alloc()
893 INIT_LIST_HEAD(&ah->txbuf); in ath5k_desc_alloc()
894 ah->txbuf_len = ATH_TXBUF; in ath5k_desc_alloc()
898 list_add_tail(&bf->list, &ah->txbuf); in ath5k_desc_alloc()
902 INIT_LIST_HEAD(&ah->bcbuf); in ath5k_desc_alloc()
906 list_add_tail(&bf->list, &ah->bcbuf); in ath5k_desc_alloc()
911 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); in ath5k_desc_alloc()
913 ah->desc = NULL; in ath5k_desc_alloc()
918 ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) in ath5k_txbuf_free_skb() argument
923 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len, in ath5k_txbuf_free_skb()
925 ieee80211_free_txskb(ah->hw, bf->skb); in ath5k_txbuf_free_skb()
932 ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) in ath5k_rxbuf_free_skb() argument
934 struct ath_common *common = ath5k_hw_common(ah); in ath5k_rxbuf_free_skb()
939 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize, in ath5k_rxbuf_free_skb()
948 ath5k_desc_free(struct ath5k_hw *ah) in ath5k_desc_free() argument
952 list_for_each_entry(bf, &ah->txbuf, list) in ath5k_desc_free()
953 ath5k_txbuf_free_skb(ah, bf); in ath5k_desc_free()
954 list_for_each_entry(bf, &ah->rxbuf, list) in ath5k_desc_free()
955 ath5k_rxbuf_free_skb(ah, bf); in ath5k_desc_free()
956 list_for_each_entry(bf, &ah->bcbuf, list) in ath5k_desc_free()
957 ath5k_txbuf_free_skb(ah, bf); in ath5k_desc_free()
960 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); in ath5k_desc_free()
961 ah->desc = NULL; in ath5k_desc_free()
962 ah->desc_daddr = 0; in ath5k_desc_free()
964 kfree(ah->bufptr); in ath5k_desc_free()
965 ah->bufptr = NULL; in ath5k_desc_free()
974 ath5k_txq_setup(struct ath5k_hw *ah, in ath5k_txq_setup() argument
1002 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); in ath5k_txq_setup()
1010 txq = &ah->txqs[qnum]; in ath5k_txq_setup()
1022 return &ah->txqs[qnum]; in ath5k_txq_setup()
1026 ath5k_beaconq_setup(struct ath5k_hw *ah) in ath5k_beaconq_setup() argument
1038 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); in ath5k_beaconq_setup()
1042 ath5k_beaconq_config(struct ath5k_hw *ah) in ath5k_beaconq_config() argument
1047 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi); in ath5k_beaconq_config()
1051 if (ah->opmode == NL80211_IFTYPE_AP || in ath5k_beaconq_config()
1052 ah->opmode == NL80211_IFTYPE_MESH_POINT) { in ath5k_beaconq_config()
1060 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) { in ath5k_beaconq_config()
1069 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beaconq_config()
1073 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi); in ath5k_beaconq_config()
1075 ATH5K_ERR(ah, "%s: unable to update parameters for beacon " in ath5k_beaconq_config()
1079 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */ in ath5k_beaconq_config()
1084 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); in ath5k_beaconq_config()
1088 qi.tqi_ready_time = (ah->bintval * 80) / 100; in ath5k_beaconq_config()
1089 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); in ath5k_beaconq_config()
1093 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); in ath5k_beaconq_config()
1110 ath5k_drain_tx_buffs(struct ath5k_hw *ah) in ath5k_drain_tx_buffs() argument
1116 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { in ath5k_drain_tx_buffs()
1117 if (ah->txqs[i].setup) { in ath5k_drain_tx_buffs()
1118 txq = &ah->txqs[i]; in ath5k_drain_tx_buffs()
1121 ath5k_debug_printtxbuf(ah, bf); in ath5k_drain_tx_buffs()
1123 ath5k_txbuf_free_skb(ah, bf); in ath5k_drain_tx_buffs()
1125 spin_lock(&ah->txbuflock); in ath5k_drain_tx_buffs()
1126 list_move_tail(&bf->list, &ah->txbuf); in ath5k_drain_tx_buffs()
1127 ah->txbuf_len++; in ath5k_drain_tx_buffs()
1129 spin_unlock(&ah->txbuflock); in ath5k_drain_tx_buffs()
1139 ath5k_txq_release(struct ath5k_hw *ah) in ath5k_txq_release() argument
1141 struct ath5k_txq *txq = ah->txqs; in ath5k_txq_release()
1144 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++) in ath5k_txq_release()
1146 ath5k_hw_release_tx_queue(ah, txq->qnum); in ath5k_txq_release()
1160 ath5k_rx_start(struct ath5k_hw *ah) in ath5k_rx_start() argument
1162 struct ath_common *common = ath5k_hw_common(ah); in ath5k_rx_start()
1168 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", in ath5k_rx_start()
1171 spin_lock_bh(&ah->rxbuflock); in ath5k_rx_start()
1172 ah->rxlink = NULL; in ath5k_rx_start()
1173 list_for_each_entry(bf, &ah->rxbuf, list) { in ath5k_rx_start()
1174 ret = ath5k_rxbuf_setup(ah, bf); in ath5k_rx_start()
1176 spin_unlock_bh(&ah->rxbuflock); in ath5k_rx_start()
1180 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); in ath5k_rx_start()
1181 ath5k_hw_set_rxdp(ah, bf->daddr); in ath5k_rx_start()
1182 spin_unlock_bh(&ah->rxbuflock); in ath5k_rx_start()
1184 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ in ath5k_rx_start()
1185 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */ in ath5k_rx_start()
1186 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ in ath5k_rx_start()
1201 ath5k_rx_stop(struct ath5k_hw *ah) in ath5k_rx_stop() argument
1204 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ in ath5k_rx_stop()
1205 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ in ath5k_rx_stop()
1207 ath5k_debug_printrxbuffs(ah); in ath5k_rx_stop()
1211 ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb, in ath5k_rx_decrypted() argument
1214 struct ath_common *common = ath5k_hw_common(ah); in ath5k_rx_decrypted()
1240 ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb, in ath5k_check_ibss_tsf() argument
1253 tsf = ath5k_hw_get_tsf64(ah); in ath5k_check_ibss_tsf()
1257 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_check_ibss_tsf()
1276 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_check_ibss_tsf()
1289 if (hw_tu >= ah->nexttbtt) in ath5k_check_ibss_tsf()
1290 ath5k_beacon_update_timers(ah, bc_tstamp); in ath5k_check_ibss_tsf()
1295 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) { in ath5k_check_ibss_tsf()
1296 ath5k_beacon_update_timers(ah, bc_tstamp); in ath5k_check_ibss_tsf()
1297 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_check_ibss_tsf()
1371 ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb, in ath5k_receive_frame() argument
1375 struct ath_common *common = ath5k_hw_common(ah); in ath5k_receive_frame()
1397 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp); in ath5k_receive_frame()
1400 rxs->freq = ah->curchan->center_freq; in ath5k_receive_frame()
1401 rxs->band = ah->curchan->band; in ath5k_receive_frame()
1403 rxs->signal = ah->ah_noise_floor + rs->rs_rssi; in ath5k_receive_frame()
1408 ah->stats.antenna_rx[rs->rs_antenna]++; in ath5k_receive_frame()
1410 ah->stats.antenna_rx[0]++; /* invalid */ in ath5k_receive_frame()
1412 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate); in ath5k_receive_frame()
1413 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs); in ath5k_receive_frame()
1414 switch (ah->ah_bwmode) { in ath5k_receive_frame()
1426 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short) in ath5k_receive_frame()
1429 trace_ath5k_rx(ah, skb); in ath5k_receive_frame()
1432 ewma_beacon_rssi_add(&ah->ah_beacon_rssi_avg, rs->rs_rssi); in ath5k_receive_frame()
1435 if (ah->opmode == NL80211_IFTYPE_ADHOC) in ath5k_receive_frame()
1436 ath5k_check_ibss_tsf(ah, skb, rxs); in ath5k_receive_frame()
1439 ieee80211_rx(ah->hw, skb); in ath5k_receive_frame()
1448 ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs) in ath5k_receive_frame_ok() argument
1450 ah->stats.rx_all_count++; in ath5k_receive_frame_ok()
1451 ah->stats.rx_bytes_count += rs->rs_datalen; in ath5k_receive_frame_ok()
1457 ah->stats.rxerr_crc++; in ath5k_receive_frame_ok()
1459 ah->stats.rxerr_fifo++; in ath5k_receive_frame_ok()
1461 ah->stats.rxerr_phy++; in ath5k_receive_frame_ok()
1463 ah->stats.rxerr_phy_code[rs->rs_phyerr]++; in ath5k_receive_frame_ok()
1490 ah->stats.rxerr_decrypt++; in ath5k_receive_frame_ok()
1496 ah->stats.rxerr_mic++; in ath5k_receive_frame_ok()
1505 if (ah->fif_filter_flags & FIF_FCSFAIL) in ath5k_receive_frame_ok()
1513 ah->stats.rxerr_jumbo++; in ath5k_receive_frame_ok()
1520 ath5k_set_current_imask(struct ath5k_hw *ah) in ath5k_set_current_imask() argument
1525 if (test_bit(ATH_STAT_RESET, ah->status)) in ath5k_set_current_imask()
1528 spin_lock_irqsave(&ah->irqlock, flags); in ath5k_set_current_imask()
1529 imask = ah->imask; in ath5k_set_current_imask()
1530 if (ah->rx_pending) in ath5k_set_current_imask()
1532 if (ah->tx_pending) in ath5k_set_current_imask()
1534 ath5k_hw_set_imr(ah, imask); in ath5k_set_current_imask()
1535 spin_unlock_irqrestore(&ah->irqlock, flags); in ath5k_set_current_imask()
1544 struct ath5k_hw *ah = from_tasklet(ah, t, rxtq); in ath5k_tasklet_rx() local
1545 struct ath_common *common = ath5k_hw_common(ah); in ath5k_tasklet_rx()
1550 spin_lock(&ah->rxbuflock); in ath5k_tasklet_rx()
1551 if (list_empty(&ah->rxbuf)) { in ath5k_tasklet_rx()
1552 ATH5K_WARN(ah, "empty rx buf pool\n"); in ath5k_tasklet_rx()
1556 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); in ath5k_tasklet_rx()
1562 if (ath5k_hw_get_rxdp(ah) == bf->daddr) in ath5k_tasklet_rx()
1565 ret = ah->ah_proc_rx_desc(ah, ds, &rs); in ath5k_tasklet_rx()
1569 ATH5K_ERR(ah, "error in processing rx descriptor\n"); in ath5k_tasklet_rx()
1570 ah->stats.rxerr_proc++; in ath5k_tasklet_rx()
1574 if (ath5k_receive_frame_ok(ah, &rs)) { in ath5k_tasklet_rx()
1575 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr); in ath5k_tasklet_rx()
1584 dma_unmap_single(ah->dev, bf->skbaddr, in ath5k_tasklet_rx()
1590 ath5k_receive_frame(ah, skb, &rs); in ath5k_tasklet_rx()
1596 list_move_tail(&bf->list, &ah->rxbuf); in ath5k_tasklet_rx()
1597 } while (ath5k_rxbuf_setup(ah, bf) == 0); in ath5k_tasklet_rx()
1599 spin_unlock(&ah->rxbuflock); in ath5k_tasklet_rx()
1600 ah->rx_pending = false; in ath5k_tasklet_rx()
1601 ath5k_set_current_imask(ah); in ath5k_tasklet_rx()
1613 struct ath5k_hw *ah = hw->priv; in ath5k_tx_queue() local
1618 trace_ath5k_tx(ah, skb, txq); in ath5k_tx_queue()
1626 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough" in ath5k_tx_queue()
1635 spin_lock_irqsave(&ah->txbuflock, flags); in ath5k_tx_queue()
1636 if (list_empty(&ah->txbuf)) { in ath5k_tx_queue()
1637 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n"); in ath5k_tx_queue()
1638 spin_unlock_irqrestore(&ah->txbuflock, flags); in ath5k_tx_queue()
1642 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list); in ath5k_tx_queue()
1644 ah->txbuf_len--; in ath5k_tx_queue()
1645 if (list_empty(&ah->txbuf)) in ath5k_tx_queue()
1647 spin_unlock_irqrestore(&ah->txbuflock, flags); in ath5k_tx_queue()
1651 if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) { in ath5k_tx_queue()
1653 spin_lock_irqsave(&ah->txbuflock, flags); in ath5k_tx_queue()
1654 list_add_tail(&bf->list, &ah->txbuf); in ath5k_tx_queue()
1655 ah->txbuf_len++; in ath5k_tx_queue()
1656 spin_unlock_irqrestore(&ah->txbuflock, flags); in ath5k_tx_queue()
1666 ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb, in ath5k_tx_frame_completed() argument
1675 ah->stats.tx_all_count++; in ath5k_tx_frame_completed()
1676 ah->stats.tx_bytes_count += skb->len; in ath5k_tx_frame_completed()
1699 ah->stats.ack_fail++; in ath5k_tx_frame_completed()
1702 ah->stats.txerr_filt++; in ath5k_tx_frame_completed()
1705 ah->stats.txerr_retry++; in ath5k_tx_frame_completed()
1707 ah->stats.txerr_fifo++; in ath5k_tx_frame_completed()
1723 ah->stats.antenna_tx[ts->ts_antenna]++; in ath5k_tx_frame_completed()
1725 ah->stats.antenna_tx[0]++; /* invalid */ in ath5k_tx_frame_completed()
1727 trace_ath5k_tx_complete(ah, skb, txq, ts); in ath5k_tx_frame_completed()
1728 ieee80211_tx_status(ah->hw, skb); in ath5k_tx_frame_completed()
1732 ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq) in ath5k_tx_processq() argument
1749 ret = ah->ah_proc_tx_desc(ah, ds, &ts); in ath5k_tx_processq()
1753 ATH5K_ERR(ah, in ath5k_tx_processq()
1762 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, in ath5k_tx_processq()
1764 ath5k_tx_frame_completed(ah, skb, txq, &ts, bf); in ath5k_tx_processq()
1773 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) { in ath5k_tx_processq()
1774 spin_lock(&ah->txbuflock); in ath5k_tx_processq()
1775 list_move_tail(&bf->list, &ah->txbuf); in ath5k_tx_processq()
1776 ah->txbuf_len++; in ath5k_tx_processq()
1778 spin_unlock(&ah->txbuflock); in ath5k_tx_processq()
1783 ieee80211_wake_queue(ah->hw, txq->qnum); in ath5k_tx_processq()
1790 struct ath5k_hw *ah = from_tasklet(ah, t, txtq); in ath5k_tasklet_tx() local
1793 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i))) in ath5k_tasklet_tx()
1794 ath5k_tx_processq(ah, &ah->txqs[i]); in ath5k_tasklet_tx()
1796 ah->tx_pending = false; in ath5k_tasklet_tx()
1797 ath5k_set_current_imask(ah); in ath5k_tasklet_tx()
1809 ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) in ath5k_beacon_setup() argument
1819 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, in ath5k_beacon_setup()
1821 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " in ath5k_beacon_setup()
1825 if (dma_mapping_error(ah->dev, bf->skbaddr)) { in ath5k_beacon_setup()
1826 ATH5K_ERR(ah, "beacon DMA mapping failed\n"); in ath5k_beacon_setup()
1833 antenna = ah->ah_tx_ant; in ath5k_beacon_setup()
1836 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { in ath5k_beacon_setup()
1860 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) in ath5k_beacon_setup()
1861 antenna = ah->bsent & 4 ? 2 : 1; in ath5k_beacon_setup()
1868 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, in ath5k_beacon_setup()
1871 (ah->ah_txpower.txp_requested * 2), in ath5k_beacon_setup()
1872 ieee80211_get_tx_rate(ah->hw, info)->hw_value, in ath5k_beacon_setup()
1880 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); in ath5k_beacon_setup()
1895 struct ath5k_hw *ah = hw->priv; in ath5k_beacon_update() local
1912 ath5k_txbuf_free_skb(ah, avf->bbuf); in ath5k_beacon_update()
1914 ret = ath5k_beacon_setup(ah, avf->bbuf); in ath5k_beacon_update()
1928 ath5k_beacon_send(struct ath5k_hw *ah) in ath5k_beacon_send() argument
1936 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n"); in ath5k_beacon_send()
1945 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) { in ath5k_beacon_send()
1946 ah->bmisscount++; in ath5k_beacon_send()
1947 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_send()
1948 "missed %u consecutive beacons\n", ah->bmisscount); in ath5k_beacon_send()
1949 if (ah->bmisscount > 10) { /* NB: 10 is a guess */ in ath5k_beacon_send()
1950 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_send()
1952 ah->bmisscount); in ath5k_beacon_send()
1953 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_beacon_send()
1955 ieee80211_queue_work(ah->hw, &ah->reset_work); in ath5k_beacon_send()
1959 if (unlikely(ah->bmisscount != 0)) { in ath5k_beacon_send()
1960 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_send()
1962 ah->bmisscount); in ath5k_beacon_send()
1963 ah->bmisscount = 0; in ath5k_beacon_send()
1966 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs + in ath5k_beacon_send()
1967 ah->num_mesh_vifs > 1) || in ath5k_beacon_send()
1968 ah->opmode == NL80211_IFTYPE_MESH_POINT) { in ath5k_beacon_send()
1969 u64 tsf = ath5k_hw_get_tsf64(ah); in ath5k_beacon_send()
1971 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval; in ath5k_beacon_send()
1972 vif = ah->bslot[(slot + 1) % ATH_BCBUF]; in ath5k_beacon_send()
1973 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_send()
1975 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif); in ath5k_beacon_send()
1977 vif = ah->bslot[0]; in ath5k_beacon_send()
1990 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) { in ath5k_beacon_send()
1991 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq); in ath5k_beacon_send()
1996 if (ah->opmode == NL80211_IFTYPE_AP || in ath5k_beacon_send()
1997 ah->opmode == NL80211_IFTYPE_MESH_POINT) { in ath5k_beacon_send()
1998 err = ath5k_beacon_update(ah->hw, vif); in ath5k_beacon_send()
2003 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION || in ath5k_beacon_send()
2004 ah->opmode == NL80211_IFTYPE_MONITOR)) { in ath5k_beacon_send()
2005 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb); in ath5k_beacon_send()
2009 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]); in ath5k_beacon_send()
2011 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr); in ath5k_beacon_send()
2012 ath5k_hw_start_tx_dma(ah, ah->bhalq); in ath5k_beacon_send()
2013 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", in ath5k_beacon_send()
2014 ah->bhalq, (unsigned long long)bf->daddr, bf->desc); in ath5k_beacon_send()
2016 skb = ieee80211_get_buffered_bc(ah->hw, vif); in ath5k_beacon_send()
2018 ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL); in ath5k_beacon_send()
2020 if (ah->cabq->txq_len >= ah->cabq->txq_max) in ath5k_beacon_send()
2023 skb = ieee80211_get_buffered_bc(ah->hw, vif); in ath5k_beacon_send()
2026 ah->bsent++; in ath5k_beacon_send()
2046 ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf) in ath5k_beacon_update_timers() argument
2051 intval = ah->bintval & AR5K_BEACON_PERIOD; in ath5k_beacon_update_timers()
2052 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs in ath5k_beacon_update_timers()
2053 + ah->num_mesh_vifs > 1) { in ath5k_beacon_update_timers()
2056 ATH5K_WARN(ah, "intval %u is too low, min 15\n", in ath5k_beacon_update_timers()
2066 hw_tsf = ath5k_hw_get_tsf64(ah); in ath5k_beacon_update_timers()
2095 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2110 ah->nexttbtt = nexttbtt; in ath5k_beacon_update_timers()
2113 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval); in ath5k_beacon_update_timers()
2120 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2123 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2126 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2129 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2133 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", in ath5k_beacon_update_timers()
2148 ath5k_beacon_config(struct ath5k_hw *ah) in ath5k_beacon_config() argument
2150 spin_lock_bh(&ah->block); in ath5k_beacon_config()
2151 ah->bmisscount = 0; in ath5k_beacon_config()
2152 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); in ath5k_beacon_config()
2154 if (ah->enable_beacon) { in ath5k_beacon_config()
2162 ath5k_beaconq_config(ah); in ath5k_beacon_config()
2164 ah->imask |= AR5K_INT_SWBA; in ath5k_beacon_config()
2166 if (ah->opmode == NL80211_IFTYPE_ADHOC) { in ath5k_beacon_config()
2167 if (ath5k_hw_hasveol(ah)) in ath5k_beacon_config()
2168 ath5k_beacon_send(ah); in ath5k_beacon_config()
2170 ath5k_beacon_update_timers(ah, -1); in ath5k_beacon_config()
2172 ath5k_hw_stop_beacon_queue(ah, ah->bhalq); in ath5k_beacon_config()
2175 ath5k_hw_set_imr(ah, ah->imask); in ath5k_beacon_config()
2176 spin_unlock_bh(&ah->block); in ath5k_beacon_config()
2181 struct ath5k_hw *ah = from_tasklet(ah, t, beacontq); in ath5k_tasklet_beacon() local
2191 if (ah->opmode == NL80211_IFTYPE_ADHOC) { in ath5k_tasklet_beacon()
2193 u64 tsf = ath5k_hw_get_tsf64(ah); in ath5k_tasklet_beacon()
2194 ah->nexttbtt += ah->bintval; in ath5k_tasklet_beacon()
2195 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_tasklet_beacon()
2198 ah->nexttbtt, in ath5k_tasklet_beacon()
2202 spin_lock(&ah->block); in ath5k_tasklet_beacon()
2203 ath5k_beacon_send(ah); in ath5k_tasklet_beacon()
2204 spin_unlock(&ah->block); in ath5k_tasklet_beacon()
2214 ath5k_intr_calibration_poll(struct ath5k_hw *ah) in ath5k_intr_calibration_poll() argument
2216 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && in ath5k_intr_calibration_poll()
2217 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && in ath5k_intr_calibration_poll()
2218 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { in ath5k_intr_calibration_poll()
2222 ah->ah_cal_next_ani = jiffies + in ath5k_intr_calibration_poll()
2224 tasklet_schedule(&ah->ani_tasklet); in ath5k_intr_calibration_poll()
2226 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) && in ath5k_intr_calibration_poll()
2227 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && in ath5k_intr_calibration_poll()
2228 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { in ath5k_intr_calibration_poll()
2237 ah->ah_cal_next_short = jiffies + in ath5k_intr_calibration_poll()
2239 ieee80211_queue_work(ah->hw, &ah->calib_work); in ath5k_intr_calibration_poll()
2247 ath5k_schedule_rx(struct ath5k_hw *ah) in ath5k_schedule_rx() argument
2249 ah->rx_pending = true; in ath5k_schedule_rx()
2250 tasklet_schedule(&ah->rxtq); in ath5k_schedule_rx()
2254 ath5k_schedule_tx(struct ath5k_hw *ah) in ath5k_schedule_tx() argument
2256 ah->tx_pending = true; in ath5k_schedule_tx()
2257 tasklet_schedule(&ah->txtq); in ath5k_schedule_tx()
2263 struct ath5k_hw *ah = dev_id; in ath5k_intr() local
2278 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) || in ath5k_intr()
2279 ((ath5k_get_bus_type(ah) != ATH_AHB) && in ath5k_intr()
2280 !ath5k_hw_is_intr_pending(ah)))) in ath5k_intr()
2285 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ in ath5k_intr()
2287 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", in ath5k_intr()
2288 status, ah->imask); in ath5k_intr()
2299 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_intr()
2301 ieee80211_queue_work(ah->hw, &ah->reset_work); in ath5k_intr()
2318 ah->stats.rxorn_intr++; in ath5k_intr()
2320 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { in ath5k_intr()
2321 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_intr()
2323 ieee80211_queue_work(ah->hw, &ah->reset_work); in ath5k_intr()
2325 ath5k_schedule_rx(ah); in ath5k_intr()
2331 tasklet_hi_schedule(&ah->beacontq); in ath5k_intr()
2341 ah->stats.rxeol_intr++; in ath5k_intr()
2346 ath5k_hw_update_tx_triglevel(ah, true); in ath5k_intr()
2350 ath5k_schedule_rx(ah); in ath5k_intr()
2357 ath5k_schedule_tx(ah); in ath5k_intr()
2365 ah->stats.mib_intr++; in ath5k_intr()
2366 ath5k_hw_update_mib_counters(ah); in ath5k_intr()
2367 ath5k_ani_mib_intr(ah); in ath5k_intr()
2372 tasklet_schedule(&ah->rf_kill.toggleq); in ath5k_intr()
2376 if (ath5k_get_bus_type(ah) == ATH_AHB) in ath5k_intr()
2379 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); in ath5k_intr()
2387 if (ah->rx_pending || ah->tx_pending) in ath5k_intr()
2388 ath5k_set_current_imask(ah); in ath5k_intr()
2391 ATH5K_WARN(ah, "too many interrupts, giving up for now\n"); in ath5k_intr()
2394 ath5k_intr_calibration_poll(ah); in ath5k_intr()
2406 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, in ath5k_calibrate_work() local
2410 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { in ath5k_calibrate_work()
2412 ah->ah_cal_next_full = jiffies + in ath5k_calibrate_work()
2414 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; in ath5k_calibrate_work()
2416 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_calibrate_work()
2419 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { in ath5k_calibrate_work()
2424 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_calibrate_work()
2426 ieee80211_queue_work(ah->hw, &ah->reset_work); in ath5k_calibrate_work()
2429 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT; in ath5k_calibrate_work()
2432 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", in ath5k_calibrate_work()
2433 ieee80211_frequency_to_channel(ah->curchan->center_freq), in ath5k_calibrate_work()
2434 ah->curchan->hw_value); in ath5k_calibrate_work()
2436 if (ath5k_hw_phy_calibrate(ah, ah->curchan)) in ath5k_calibrate_work()
2437 ATH5K_ERR(ah, "calibration of channel %u failed\n", in ath5k_calibrate_work()
2439 ah->curchan->center_freq)); in ath5k_calibrate_work()
2442 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) in ath5k_calibrate_work()
2443 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; in ath5k_calibrate_work()
2444 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT) in ath5k_calibrate_work()
2445 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT; in ath5k_calibrate_work()
2452 struct ath5k_hw *ah = from_tasklet(ah, t, ani_tasklet); in ath5k_tasklet_ani() local
2454 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; in ath5k_tasklet_ani()
2455 ath5k_ani_calibration(ah); in ath5k_tasklet_ani()
2456 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; in ath5k_tasklet_ani()
2463 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, in ath5k_tx_complete_poll_work() local
2469 if (!test_bit(ATH_STAT_STARTED, ah->status)) in ath5k_tx_complete_poll_work()
2472 mutex_lock(&ah->lock); in ath5k_tx_complete_poll_work()
2474 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { in ath5k_tx_complete_poll_work()
2475 if (ah->txqs[i].setup) { in ath5k_tx_complete_poll_work()
2476 txq = &ah->txqs[i]; in ath5k_tx_complete_poll_work()
2480 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT, in ath5k_tx_complete_poll_work()
2496 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_tx_complete_poll_work()
2498 ath5k_reset(ah, NULL, true); in ath5k_tx_complete_poll_work()
2501 mutex_unlock(&ah->lock); in ath5k_tx_complete_poll_work()
2503 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, in ath5k_tx_complete_poll_work()
2529 ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops) in ath5k_init_ah() argument
2531 struct ieee80211_hw *hw = ah->hw; in ath5k_init_ah()
2537 SET_IEEE80211_DEV(hw, ah->dev); in ath5k_init_ah()
2571 __set_bit(ATH_STAT_INVALID, ah->status); in ath5k_init_ah()
2573 ah->opmode = NL80211_IFTYPE_STATION; in ath5k_init_ah()
2574 ah->bintval = 1000; in ath5k_init_ah()
2575 mutex_init(&ah->lock); in ath5k_init_ah()
2576 spin_lock_init(&ah->rxbuflock); in ath5k_init_ah()
2577 spin_lock_init(&ah->txbuflock); in ath5k_init_ah()
2578 spin_lock_init(&ah->block); in ath5k_init_ah()
2579 spin_lock_init(&ah->irqlock); in ath5k_init_ah()
2582 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah); in ath5k_init_ah()
2584 ATH5K_ERR(ah, "request_irq failed\n"); in ath5k_init_ah()
2588 common = ath5k_hw_common(ah); in ath5k_init_ah()
2591 common->ah = ah; in ath5k_init_ah()
2593 common->priv = ah; in ath5k_init_ah()
2606 ret = ath5k_hw_init(ah); in ath5k_init_ah()
2611 if (ah->ah_capabilities.cap_has_mrr_support) { in ath5k_init_ah()
2624 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", in ath5k_init_ah()
2625 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev), in ath5k_init_ah()
2626 ah->ah_mac_srev, in ath5k_init_ah()
2627 ah->ah_phy_revision); in ath5k_init_ah()
2629 if (!ah->ah_single_chip) { in ath5k_init_ah()
2631 if (ah->ah_radio_5ghz_revision && in ath5k_init_ah()
2632 !ah->ah_radio_2ghz_revision) { in ath5k_init_ah()
2635 ah->ah_capabilities.cap_mode)) { in ath5k_init_ah()
2636 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", in ath5k_init_ah()
2638 ah->ah_radio_5ghz_revision), in ath5k_init_ah()
2639 ah->ah_radio_5ghz_revision); in ath5k_init_ah()
2643 ah->ah_capabilities.cap_mode)) { in ath5k_init_ah()
2644 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", in ath5k_init_ah()
2646 ah->ah_radio_5ghz_revision), in ath5k_init_ah()
2647 ah->ah_radio_5ghz_revision); in ath5k_init_ah()
2650 ATH5K_INFO(ah, "RF%s multiband radio found" in ath5k_init_ah()
2653 ah->ah_radio_5ghz_revision), in ath5k_init_ah()
2654 ah->ah_radio_5ghz_revision); in ath5k_init_ah()
2659 else if (ah->ah_radio_5ghz_revision && in ath5k_init_ah()
2660 ah->ah_radio_2ghz_revision) { in ath5k_init_ah()
2661 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", in ath5k_init_ah()
2663 ah->ah_radio_5ghz_revision), in ath5k_init_ah()
2664 ah->ah_radio_5ghz_revision); in ath5k_init_ah()
2665 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", in ath5k_init_ah()
2667 ah->ah_radio_2ghz_revision), in ath5k_init_ah()
2668 ah->ah_radio_2ghz_revision); in ath5k_init_ah()
2672 ath5k_debug_init_device(ah); in ath5k_init_ah()
2675 __clear_bit(ATH_STAT_INVALID, ah->status); in ath5k_init_ah()
2679 ath5k_hw_deinit(ah); in ath5k_init_ah()
2681 free_irq(ah->irq, ah); in ath5k_init_ah()
2687 ath5k_stop_locked(struct ath5k_hw *ah) in ath5k_stop_locked() argument
2690 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n", in ath5k_stop_locked()
2691 test_bit(ATH_STAT_INVALID, ah->status)); in ath5k_stop_locked()
2708 ieee80211_stop_queues(ah->hw); in ath5k_stop_locked()
2710 if (!test_bit(ATH_STAT_INVALID, ah->status)) { in ath5k_stop_locked()
2711 ath5k_led_off(ah); in ath5k_stop_locked()
2712 ath5k_hw_set_imr(ah, 0); in ath5k_stop_locked()
2713 synchronize_irq(ah->irq); in ath5k_stop_locked()
2714 ath5k_rx_stop(ah); in ath5k_stop_locked()
2715 ath5k_hw_dma_stop(ah); in ath5k_stop_locked()
2716 ath5k_drain_tx_buffs(ah); in ath5k_stop_locked()
2717 ath5k_hw_phy_disable(ah); in ath5k_stop_locked()
2725 struct ath5k_hw *ah = hw->priv; in ath5k_start() local
2726 struct ath_common *common = ath5k_hw_common(ah); in ath5k_start()
2729 mutex_lock(&ah->lock); in ath5k_start()
2731 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode); in ath5k_start()
2737 ath5k_stop_locked(ah); in ath5k_start()
2746 ah->curchan = ah->hw->conf.chandef.chan; in ath5k_start()
2747 ah->imask = AR5K_INT_RXOK in ath5k_start()
2757 ret = ath5k_reset(ah, NULL, false); in ath5k_start()
2762 ath5k_rfkill_hw_start(ah); in ath5k_start()
2773 ah->ah_ack_bitrate_high = true; in ath5k_start()
2775 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++) in ath5k_start()
2776 ah->bslot[i] = NULL; in ath5k_start()
2780 mutex_unlock(&ah->lock); in ath5k_start()
2782 set_bit(ATH_STAT_STARTED, ah->status); in ath5k_start()
2783 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, in ath5k_start()
2789 static void ath5k_stop_tasklets(struct ath5k_hw *ah) in ath5k_stop_tasklets() argument
2791 ah->rx_pending = false; in ath5k_stop_tasklets()
2792 ah->tx_pending = false; in ath5k_stop_tasklets()
2793 tasklet_kill(&ah->rxtq); in ath5k_stop_tasklets()
2794 tasklet_kill(&ah->txtq); in ath5k_stop_tasklets()
2795 tasklet_kill(&ah->beacontq); in ath5k_stop_tasklets()
2796 tasklet_kill(&ah->ani_tasklet); in ath5k_stop_tasklets()
2807 struct ath5k_hw *ah = hw->priv; in ath5k_stop() local
2810 mutex_lock(&ah->lock); in ath5k_stop()
2811 ret = ath5k_stop_locked(ah); in ath5k_stop()
2812 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) { in ath5k_stop()
2833 ret = ath5k_hw_on_hold(ah); in ath5k_stop()
2835 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_stop()
2839 mutex_unlock(&ah->lock); in ath5k_stop()
2841 ath5k_stop_tasklets(ah); in ath5k_stop()
2843 clear_bit(ATH_STAT_STARTED, ah->status); in ath5k_stop()
2844 cancel_delayed_work_sync(&ah->tx_complete_work); in ath5k_stop()
2847 ath5k_rfkill_hw_stop(ah); in ath5k_stop()
2857 ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, in ath5k_reset() argument
2860 struct ath_common *common = ath5k_hw_common(ah); in ath5k_reset()
2864 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n"); in ath5k_reset()
2866 __set_bit(ATH_STAT_RESET, ah->status); in ath5k_reset()
2868 ath5k_hw_set_imr(ah, 0); in ath5k_reset()
2869 synchronize_irq(ah->irq); in ath5k_reset()
2870 ath5k_stop_tasklets(ah); in ath5k_reset()
2875 ani_mode = ah->ani_state.ani_mode; in ath5k_reset()
2876 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); in ath5k_reset()
2881 ath5k_drain_tx_buffs(ah); in ath5k_reset()
2884 ath5k_hw_stop_rx_pcu(ah); in ath5k_reset()
2891 ret = ath5k_hw_dma_stop(ah); in ath5k_reset()
2897 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_reset()
2903 ah->curchan = chan; in ath5k_reset()
2905 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu); in ath5k_reset()
2907 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret); in ath5k_reset()
2911 ret = ath5k_rx_start(ah); in ath5k_reset()
2913 ATH5K_ERR(ah, "can't start recv logic\n"); in ath5k_reset()
2917 ath5k_ani_init(ah, ani_mode); in ath5k_reset()
2930 ah->ah_cal_next_full = jiffies + in ath5k_reset()
2932 ah->ah_cal_next_ani = jiffies + in ath5k_reset()
2934 ah->ah_cal_next_short = jiffies + in ath5k_reset()
2937 ewma_beacon_rssi_init(&ah->ah_beacon_rssi_avg); in ath5k_reset()
2940 memset(&ah->survey, 0, sizeof(ah->survey)); in ath5k_reset()
2958 __clear_bit(ATH_STAT_RESET, ah->status); in ath5k_reset()
2960 ath5k_beacon_config(ah); in ath5k_reset()
2963 ieee80211_wake_queues(ah->hw); in ath5k_reset()
2972 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, in ath5k_reset_work() local
2975 mutex_lock(&ah->lock); in ath5k_reset_work()
2976 ath5k_reset(ah, NULL, true); in ath5k_reset_work()
2977 mutex_unlock(&ah->lock); in ath5k_reset_work()
2984 struct ath5k_hw *ah = hw->priv; in ath5k_init() local
2985 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); in ath5k_init()
2999 ATH5K_ERR(ah, "can't get channels\n"); in ath5k_init()
3006 ret = ath5k_desc_alloc(ah); in ath5k_init()
3008 ATH5K_ERR(ah, "can't allocate descriptors\n"); in ath5k_init()
3018 ret = ath5k_beaconq_setup(ah); in ath5k_init()
3020 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n"); in ath5k_init()
3023 ah->bhalq = ret; in ath5k_init()
3024 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0); in ath5k_init()
3025 if (IS_ERR(ah->cabq)) { in ath5k_init()
3026 ATH5K_ERR(ah, "can't setup cab queue\n"); in ath5k_init()
3027 ret = PTR_ERR(ah->cabq); in ath5k_init()
3033 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { in ath5k_init()
3036 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); in ath5k_init()
3038 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3042 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); in ath5k_init()
3044 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3048 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); in ath5k_init()
3050 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3054 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); in ath5k_init()
3056 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3063 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); in ath5k_init()
3065 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3072 tasklet_setup(&ah->rxtq, ath5k_tasklet_rx); in ath5k_init()
3073 tasklet_setup(&ah->txtq, ath5k_tasklet_tx); in ath5k_init()
3074 tasklet_setup(&ah->beacontq, ath5k_tasklet_beacon); in ath5k_init()
3075 tasklet_setup(&ah->ani_tasklet, ath5k_tasklet_ani); in ath5k_init()
3077 INIT_WORK(&ah->reset_work, ath5k_reset_work); in ath5k_init()
3078 INIT_WORK(&ah->calib_work, ath5k_calibrate_work); in ath5k_init()
3079 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work); in ath5k_init()
3081 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); in ath5k_init()
3083 ATH5K_ERR(ah, "unable to read address from EEPROM\n"); in ath5k_init()
3089 ath5k_update_bssid_mask_and_opmode(ah, NULL); in ath5k_init()
3091 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; in ath5k_init()
3094 ATH5K_ERR(ah, "can't initialize regulatory system\n"); in ath5k_init()
3100 ATH5K_ERR(ah, "can't register ieee80211 hw\n"); in ath5k_init()
3107 ath5k_init_leds(ah); in ath5k_init()
3109 ath5k_sysfs_register(ah); in ath5k_init()
3113 ath5k_txq_release(ah); in ath5k_init()
3115 ath5k_hw_release_tx_queue(ah, ah->bhalq); in ath5k_init()
3117 ath5k_desc_free(ah); in ath5k_init()
3123 ath5k_deinit_ah(struct ath5k_hw *ah) in ath5k_deinit_ah() argument
3125 struct ieee80211_hw *hw = ah->hw; in ath5k_deinit_ah()
3141 ath5k_desc_free(ah); in ath5k_deinit_ah()
3142 ath5k_txq_release(ah); in ath5k_deinit_ah()
3143 ath5k_hw_release_tx_queue(ah, ah->bhalq); in ath5k_deinit_ah()
3144 ath5k_unregister_leds(ah); in ath5k_deinit_ah()
3146 ath5k_sysfs_unregister(ah); in ath5k_deinit_ah()
3152 ath5k_hw_deinit(ah); in ath5k_deinit_ah()
3153 free_irq(ah->irq, ah); in ath5k_deinit_ah()
3157 ath5k_any_vif_assoc(struct ath5k_hw *ah) in ath5k_any_vif_assoc() argument
3166 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, in ath5k_any_vif_assoc()
3174 struct ath5k_hw *ah = hw->priv; in ath5k_set_beacon_filter() local
3176 rfilt = ath5k_hw_get_rx_filter(ah); in ath5k_set_beacon_filter()
3181 ath5k_hw_set_rx_filter(ah, rfilt); in ath5k_set_beacon_filter()
3182 ah->filter_flags = rfilt; in ath5k_set_beacon_filter()
3185 void _ath5k_printk(const struct ath5k_hw *ah, const char *level, in _ath5k_printk() argument
3196 if (ah && ah->hw) in _ath5k_printk()
3198 level, wiphy_name(ah->hw->wiphy), &vaf); in _ath5k_printk()