18 	case 0:  in ath11k_hw_ipq8074_mac_from_pdev_id()
19 		return 0;  in ath11k_hw_ipq8074_mac_from_pdev_id()
47 	config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;  in ath11k_init_wmi_config_qca6390()
56 	config->num_mcast_groups = 0;  in ath11k_init_wmi_config_qca6390()
57 	config->num_mcast_table_elems = 0;  in ath11k_init_wmi_config_qca6390()
58 	config->mcast2ucast_mode = 0;  in ath11k_init_wmi_config_qca6390()
60 	config->num_wds_entries = 0;  in ath11k_init_wmi_config_qca6390()
61 	config->dma_burst_size = 0;  in ath11k_init_wmi_config_qca6390()
62 	config->rx_skip_defrag_timeout_dup_detection_check = 0;  in ath11k_init_wmi_config_qca6390()
65 	config->num_msdu_desc = 0x400;  in ath11k_init_wmi_config_qca6390()
69 	config->peer_map_unmap_v2_support = 0;  in ath11k_init_wmi_config_qca6390()
71 	config->max_frag_entries = 0xa;  in ath11k_init_wmi_config_qca6390()
72 	config->num_tdls_vdevs = 0x1;  in ath11k_init_wmi_config_qca6390()
74 	config->beacon_tx_offload_max_vdev = 0x2;  in ath11k_init_wmi_config_qca6390()
75 	config->num_multicast_filter_entries = 0x20;  in ath11k_init_wmi_config_qca6390()
76 	config->num_wow_filters = 0x16;  in ath11k_init_wmi_config_qca6390()
77 	config->num_keep_alive_pattern = 0;  in ath11k_init_wmi_config_qca6390()
102 	config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;  in ath11k_init_wmi_config_ipq8074()
143 	return 0;  in ath11k_hw_mac_id_to_srng_id_ipq8074()
149 	return 0;  in ath11k_hw_mac_id_to_pdev_id_qca6390()
179 #define ATH11K_TX_RING_MASK_0 0x1
180 #define ATH11K_TX_RING_MASK_1 0x2
181 #define ATH11K_TX_RING_MASK_2 0x4
183 #define ATH11K_RX_RING_MASK_0 0x1
184 #define ATH11K_RX_RING_MASK_1 0x2
185 #define ATH11K_RX_RING_MASK_2 0x4
186 #define ATH11K_RX_RING_MASK_3 0x8
188 #define ATH11K_RX_ERR_RING_MASK_0 0x1
190 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1
192 #define ATH11K_REO_STATUS_RING_MASK_0 0x1
194 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1
195 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2
196 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4
198 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1
199 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2
200 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4
202 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1
203 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2
204 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4
213 		0, 0, 0, 0,
219 		0, 0, 0, 0, 0, 0, 0,
251 		0, 0, 0, 0,
257 		0, 0, 0, 0, 0, 0, 0,
285 		.pipenum = __cpu_to_le32(0),
290 		.reserved = __cpu_to_le32(0),
300 		.reserved = __cpu_to_le32(0),
310 		.reserved = __cpu_to_le32(0),
320 		.reserved = __cpu_to_le32(0),
330 		.reserved = __cpu_to_le32(0),
339 		.flags = __cpu_to_le32(0),
340 		.reserved = __cpu_to_le32(0),
350 		.reserved = __cpu_to_le32(0),
360 		.reserved = __cpu_to_le32(0),
370 		.reserved = __cpu_to_le32(0),
380 		.reserved = __cpu_to_le32(0),
387 		.nentries = __cpu_to_le32(0),
388 		.nbytes_max = __cpu_to_le32(0),
390 		.reserved = __cpu_to_le32(0),
474 		.pipenum = __cpu_to_le32(0),
484 		.pipenum = __cpu_to_le32(0),
576 		.pipenum = __cpu_to_le32(0),
586 		.pipenum = __cpu_to_le32(0),
618 		.pipenum = __cpu_to_le32(0),
623 		.reserved = __cpu_to_le32(0),
633 		.reserved = __cpu_to_le32(0),
643 		.reserved = __cpu_to_le32(0),
653 		.reserved = __cpu_to_le32(0),
663 		.reserved = __cpu_to_le32(0),
673 		.reserved = __cpu_to_le32(0),
683 		.reserved = __cpu_to_le32(0),
690 		.nentries = __cpu_to_le32(0),
691 		.nbytes_max = __cpu_to_le32(0),
693 		.reserved = __cpu_to_le32(0),
703 		.reserved = __cpu_to_le32(0),
766 		__cpu_to_le32(0),
787 		__cpu_to_le32(0),
788 		__cpu_to_le32(0),
789 		__cpu_to_le32(0),
795 	.hal_tcl1_ring_base_lsb = 0x00000510,
796 	.hal_tcl1_ring_base_msb = 0x00000514,
797 	.hal_tcl1_ring_id = 0x00000518,
798 	.hal_tcl1_ring_misc = 0x00000520,
799 	.hal_tcl1_ring_tp_addr_lsb = 0x0000052c,
800 	.hal_tcl1_ring_tp_addr_msb = 0x00000530,
801 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540,
802 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544,
803 	.hal_tcl1_ring_msi1_base_lsb = 0x00000558,
804 	.hal_tcl1_ring_msi1_base_msb = 0x0000055c,
805 	.hal_tcl1_ring_msi1_data = 0x00000560,
806 	.hal_tcl2_ring_base_lsb = 0x00000568,
807 	.hal_tcl_ring_base_lsb = 0x00000618,
810 	.hal_tcl_status_ring_base_lsb = 0x00000720,
813 	.hal_reo1_ring_base_lsb = 0x0000029c,
814 	.hal_reo1_ring_base_msb = 0x000002a0,
815 	.hal_reo1_ring_id = 0x000002a4,
816 	.hal_reo1_ring_misc = 0x000002ac,
817 	.hal_reo1_ring_hp_addr_lsb = 0x000002b0,
818 	.hal_reo1_ring_hp_addr_msb = 0x000002b4,
819 	.hal_reo1_ring_producer_int_setup = 0x000002c0,
820 	.hal_reo1_ring_msi1_base_lsb = 0x000002e4,
821 	.hal_reo1_ring_msi1_base_msb = 0x000002e8,
822 	.hal_reo1_ring_msi1_data = 0x000002ec,
823 	.hal_reo2_ring_base_lsb = 0x000002f4,
824 	.hal_reo1_aging_thresh_ix_0 = 0x00000564,
825 	.hal_reo1_aging_thresh_ix_1 = 0x00000568,
826 	.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
827 	.hal_reo1_aging_thresh_ix_3 = 0x00000570,
830 	.hal_reo1_ring_hp = 0x00003038,
831 	.hal_reo1_ring_tp = 0x0000303c,
832 	.hal_reo2_ring_hp = 0x00003040,
835 	.hal_reo_tcl_ring_base_lsb = 0x000003fc,
836 	.hal_reo_tcl_ring_hp = 0x00003058,
839 	.hal_reo_status_ring_base_lsb = 0x00000504,
840 	.hal_reo_status_hp = 0x00003070,
846 	.hal_tcl1_ring_base_lsb = 0x00000684,
847 	.hal_tcl1_ring_base_msb = 0x00000688,
848 	.hal_tcl1_ring_id = 0x0000068c,
849 	.hal_tcl1_ring_misc = 0x00000694,
850 	.hal_tcl1_ring_tp_addr_lsb = 0x000006a0,
851 	.hal_tcl1_ring_tp_addr_msb = 0x000006a4,
852 	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4,
853 	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8,
854 	.hal_tcl1_ring_msi1_base_lsb = 0x000006cc,
855 	.hal_tcl1_ring_msi1_base_msb = 0x000006d0,
856 	.hal_tcl1_ring_msi1_data = 0x000006d4,
857 	.hal_tcl2_ring_base_lsb = 0x000006dc,
858 	.hal_tcl_ring_base_lsb = 0x0000078c,
861 	.hal_tcl_status_ring_base_lsb = 0x00000894,
864 	.hal_reo1_ring_base_lsb = 0x00000244,
865 	.hal_reo1_ring_base_msb = 0x00000248,
866 	.hal_reo1_ring_id = 0x0000024c,
867 	.hal_reo1_ring_misc = 0x00000254,
868 	.hal_reo1_ring_hp_addr_lsb = 0x00000258,
869 	.hal_reo1_ring_hp_addr_msb = 0x0000025c,
870 	.hal_reo1_ring_producer_int_setup = 0x00000268,
871 	.hal_reo1_ring_msi1_base_lsb = 0x0000028c,
872 	.hal_reo1_ring_msi1_base_msb = 0x00000290,
873 	.hal_reo1_ring_msi1_data = 0x00000294,
874 	.hal_reo2_ring_base_lsb = 0x0000029c,
875 	.hal_reo1_aging_thresh_ix_0 = 0x0000050c,
876 	.hal_reo1_aging_thresh_ix_1 = 0x00000510,
877 	.hal_reo1_aging_thresh_ix_2 = 0x00000514,
878 	.hal_reo1_aging_thresh_ix_3 = 0x00000518,
881 	.hal_reo1_ring_hp = 0x00003030,
882 	.hal_reo1_ring_tp = 0x00003034,
883 	.hal_reo2_ring_hp = 0x00003038,
886 	.hal_reo_tcl_ring_base_lsb = 0x000003a4,
887 	.hal_reo_tcl_ring_hp = 0x00003050,
890 	.hal_reo_status_ring_base_lsb = 0x000004ac,
891 	.hal_reo_status_hp = 0x00003068,