3417 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_tx_lock()
3438 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_tx_unlock()
3458 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_tx_lock()
3469 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_tx_unlock()
3489 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_handle_tx_pause()
3534 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_handle_tx_pause_vdev()
3539 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_handle_tx_pause_vdev()
3574 	if (ar->htt.target_version_major < 3 &&  in ath10k_mac_tx_h_get_txmode()
3769 	return (ar->htt.target_version_major >= 3 &&  in ath10k_mac_tx_frm_has_freq()
3770 		ar->htt.target_version_minor >= 4 &&  in ath10k_mac_tx_frm_has_freq()
3805 		else if (ar->htt.target_version_major >= 3)  in ath10k_mac_tx_h_get_txpath()
3819 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_tx_submit()  local
3824 		ret = ath10k_htt_tx(htt, txmode, skb);  in ath10k_mac_tx_submit()
3827 		ret = ath10k_htt_mgmt_tx(htt, skb);  in ath10k_mac_tx_submit()
4095 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_txq_unref()
4096 	idr_for_each_entry(&ar->htt.pending_tx, msdu, msdu_id) {  in ath10k_mac_txq_unref()
4101 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_txq_unref()
4134 	if (ar->htt.tx_q_state.mode == HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_tx_can_push()
4137 	if (ar->htt.num_pending_tx < ar->htt.tx_q_state.num_push_allowed)  in ath10k_mac_tx_can_push()
4196 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_tx_push_txq()  local
4209 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4210 	ret = ath10k_htt_tx_inc_pending(htt);  in ath10k_mac_tx_push_txq()
4211 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4218 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4219 		ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4220 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4237 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4238 		ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);  in ath10k_mac_tx_push_txq()
4241 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4242 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4245 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4252 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4253 		ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4255 			ath10k_htt_tx_mgmt_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4256 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4261 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4263 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4295 	if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_tx_push_pending()
4298 	if (ar->htt.num_pending_tx >= (ar->htt.max_num_pending_tx / 2))  in ath10k_mac_tx_push_pending()
4481 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_op_tx()  local
4505 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4508 		ret = ath10k_htt_tx_inc_pending(htt);  in ath10k_mac_op_tx()
4512 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4517 		ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);  in ath10k_mac_op_tx()
4521 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_op_tx()
4522 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4526 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4533 			spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4534 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_op_tx()
4536 				ath10k_htt_tx_mgmt_dec_pending(htt);  in ath10k_mac_op_tx()
4537 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4551 	if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_op_wake_tx_queue()
5704 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_add_interface()
5707 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_add_interface()
5855 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_remove_interface()
5857 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_remove_interface()
7902 	time_left = wait_event_timeout(ar->htt.empty_tx_wq, ({  in ath10k_mac_wait_tx_complete()
7905 			spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_wait_tx_complete()
7906 			empty = (ar->htt.num_pending_tx == 0);  in ath10k_mac_wait_tx_complete()
7907 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_wait_tx_complete()
7936 			ath10k_htt_flush_tx(&ar->htt);  in ath10k_flush()
9175 	if (ar->htt.disable_tx_comp) {  in ath10k_sta_statistics()