624 	phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1;  in ath10k_hw_qca988x_set_coverage_class()
657 	slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);  in ath10k_hw_qca988x_set_coverage_class()
671 	slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);  in ath10k_hw_qca988x_set_coverage_class()
678 	ack_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);  in ath10k_hw_qca988x_set_coverage_class()
684 	cts_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);  in ath10k_hw_qca988x_set_coverage_class()
765 	if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT)  in ath10k_hw_qca6174_enable_pll_clock()
768 	hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)];  in ath10k_hw_qca6174_enable_pll_clock()
835 		if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))  in ath10k_hw_qca6174_enable_pll_clock()
843 	if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))  in ath10k_hw_qca6174_enable_pll_clock()
866 		if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))  in ath10k_hw_qca6174_enable_pll_clock()
874 	if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING))  in ath10k_hw_qca6174_enable_pll_clock()
1139 	return MS(__le32_to_cpu(rxd->msdu_end.qca99x0.info1),  in ath10k_qca99x0_rx_desc_get_l3_pad_bytes()