Lines Matching +full:0 +full:x0007ffff
16 .rtc_soc_base_address = 0x00004000,
17 .rtc_wmac_base_address = 0x00005000,
18 .soc_core_base_address = 0x00009000,
19 .wlan_mac_base_address = 0x00020000,
20 .ce_wrapper_base_address = 0x00057000,
21 .ce0_base_address = 0x00057400,
22 .ce1_base_address = 0x00057800,
23 .ce2_base_address = 0x00057c00,
24 .ce3_base_address = 0x00058000,
25 .ce4_base_address = 0x00058400,
26 .ce5_base_address = 0x00058800,
27 .ce6_base_address = 0x00058c00,
28 .ce7_base_address = 0x00059000,
29 .soc_reset_control_si0_rst_mask = 0x00000001,
30 .soc_reset_control_ce_rst_mask = 0x00040000,
31 .soc_chip_id_address = 0x000000ec,
32 .scratch_3_address = 0x00000030,
33 .fw_indicator_address = 0x00009030,
34 .pcie_local_base_address = 0x00080000,
35 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
36 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
37 .pcie_intr_fw_mask = 0x00000400,
38 .pcie_intr_ce_mask_all = 0x0007f800,
39 .pcie_intr_clr_address = 0x00000014,
43 .rtc_soc_base_address = 0x00000800,
44 .rtc_wmac_base_address = 0x00001000,
45 .soc_core_base_address = 0x0003a000,
46 .wlan_mac_base_address = 0x00010000,
47 .ce_wrapper_base_address = 0x00034000,
48 .ce0_base_address = 0x00034400,
49 .ce1_base_address = 0x00034800,
50 .ce2_base_address = 0x00034c00,
51 .ce3_base_address = 0x00035000,
52 .ce4_base_address = 0x00035400,
53 .ce5_base_address = 0x00035800,
54 .ce6_base_address = 0x00035c00,
55 .ce7_base_address = 0x00036000,
56 .soc_reset_control_si0_rst_mask = 0x00000000,
57 .soc_reset_control_ce_rst_mask = 0x00000001,
58 .soc_chip_id_address = 0x000000f0,
59 .scratch_3_address = 0x00000028,
60 .fw_indicator_address = 0x0003a028,
61 .pcie_local_base_address = 0x00080000,
62 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
63 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
64 .pcie_intr_fw_mask = 0x00000400,
65 .pcie_intr_ce_mask_all = 0x0007f800,
66 .pcie_intr_clr_address = 0x00000014,
67 .cpu_pll_init_address = 0x00404020,
68 .cpu_speed_address = 0x00404024,
69 .core_clk_div_address = 0x00404028,
73 .rtc_soc_base_address = 0x00080000,
74 .rtc_wmac_base_address = 0x00000000,
75 .soc_core_base_address = 0x00082000,
76 .wlan_mac_base_address = 0x00030000,
77 .ce_wrapper_base_address = 0x0004d000,
78 .ce0_base_address = 0x0004a000,
79 .ce1_base_address = 0x0004a400,
80 .ce2_base_address = 0x0004a800,
81 .ce3_base_address = 0x0004ac00,
82 .ce4_base_address = 0x0004b000,
83 .ce5_base_address = 0x0004b400,
84 .ce6_base_address = 0x0004b800,
85 .ce7_base_address = 0x0004bc00,
91 * CE8 0x0004c000
92 * CE9 0x0004c400
93 * CE10 0x0004c800
94 * CE11 0x0004cc00
96 .soc_reset_control_si0_rst_mask = 0x00000001,
97 .soc_reset_control_ce_rst_mask = 0x00000100,
98 .soc_chip_id_address = 0x000000ec,
99 .scratch_3_address = 0x00040050,
100 .fw_indicator_address = 0x00040050,
101 .pcie_local_base_address = 0x00000000,
102 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
103 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
104 .pcie_intr_fw_mask = 0x00100000,
105 .pcie_intr_ce_mask_all = 0x000fff00,
106 .pcie_intr_clr_address = 0x00000010,
110 .rtc_soc_base_address = 0x00080000,
111 .soc_core_base_address = 0x00082000,
112 .wlan_mac_base_address = 0x00030000,
113 .ce_wrapper_base_address = 0x0004d000,
114 .ce0_base_address = 0x0004a000,
115 .ce1_base_address = 0x0004a400,
116 .ce2_base_address = 0x0004a800,
117 .ce3_base_address = 0x0004ac00,
118 .ce4_base_address = 0x0004b000,
119 .ce5_base_address = 0x0004b400,
120 .ce6_base_address = 0x0004b800,
121 .ce7_base_address = 0x0004bc00,
126 * CE8 0x0004c000
127 * CE9 0x0004c400
128 * CE10 0x0004c800
129 * CE11 0x0004cc00
131 .soc_reset_control_si0_rst_mask = 0x00000001,
132 .soc_reset_control_ce_rst_mask = 0x00000100,
133 .soc_chip_id_address = 0x000000ec,
134 .fw_indicator_address = 0x0004f00c,
135 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
136 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
137 .pcie_intr_fw_mask = 0x00100000,
138 .pcie_intr_ce_mask_all = 0x000fff00,
139 .pcie_intr_clr_address = 0x00000010,
147 .ce_desc_meta_data_mask = 0xFFFC,
156 .ce_desc_meta_data_mask = 0xFFFC,
159 .rfkill_cfg = 0,
168 .ce_desc_meta_data_mask = 0xFFF0,
177 .ce_desc_meta_data_mask = 0xFFF0,
184 .ce_desc_meta_data_mask = 0xFFF0,
189 .rtc_soc_base_address = 0x00000000,
190 .rtc_wmac_base_address = 0x00000000,
191 .soc_core_base_address = 0x00000000,
192 .ce_wrapper_base_address = 0x0024C000,
193 .ce0_base_address = 0x00240000,
194 .ce1_base_address = 0x00241000,
195 .ce2_base_address = 0x00242000,
196 .ce3_base_address = 0x00243000,
197 .ce4_base_address = 0x00244000,
198 .ce5_base_address = 0x00245000,
199 .ce6_base_address = 0x00246000,
200 .ce7_base_address = 0x00247000,
201 .ce8_base_address = 0x00248000,
202 .ce9_base_address = 0x00249000,
203 .ce10_base_address = 0x0024A000,
204 .ce11_base_address = 0x0024B000,
205 .soc_chip_id_address = 0x000000f0,
206 .soc_reset_control_si0_rst_mask = 0x00000001,
207 .soc_reset_control_ce_rst_mask = 0x00000100,
208 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
209 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
210 .pcie_intr_fw_mask = 0x00100000,
214 .msb = 0x00000010,
215 .lsb = 0x00000010,
220 .msb = 0x00000012,
221 .lsb = 0x00000012,
226 .msb = 0x00000000,
227 .lsb = 0x00000000,
228 .mask = GENMASK(15, 0),
232 .addr = 0x00000018,
239 .mask = GENMASK(0, 0),
247 .dstr_lmask = 0x00000010,
248 .dstr_hmask = 0x00000008,
249 .srcr_lmask = 0x00000004,
250 .srcr_hmask = 0x00000002,
251 .cc_mask = 0x00000001,
252 .wm_mask = 0x0000001E,
253 .addr = 0x00000030,
257 .axi_err = 0x00000100,
258 .dstr_add_err = 0x00000200,
259 .srcr_len_err = 0x00000100,
260 .dstr_mlen_vio = 0x00000080,
261 .dstr_overflow = 0x00000040,
262 .srcr_overflow = 0x00000020,
263 .err_mask = 0x000003E0,
264 .addr = 0x00000038,
268 .msb = 0x00000000,
269 .lsb = 0x00000010,
274 .msb = 0x0000000f,
275 .lsb = 0x00000000,
276 .mask = GENMASK(15, 0),
280 .addr = 0x0000004c,
281 .low_rst = 0x00000000,
282 .high_rst = 0x00000000,
288 .lsb = 0x00000010,
293 .msb = 0x0000000f,
294 .lsb = 0x00000000,
295 .mask = GENMASK(15, 0),
299 .addr = 0x00000050,
300 .low_rst = 0x00000000,
301 .high_rst = 0x00000000,
308 .mask = 0x00080000,
309 .enable = 0x00000000,
313 .sr_base_addr_lo = 0x00000000,
314 .sr_base_addr_hi = 0x00000004,
315 .sr_size_addr = 0x00000008,
316 .dr_base_addr_lo = 0x0000000c,
317 .dr_base_addr_hi = 0x00000010,
318 .dr_size_addr = 0x00000014,
319 .misc_ie_addr = 0x00000034,
320 .sr_wr_index_addr = 0x0000003c,
321 .dst_wr_index_addr = 0x00000040,
322 .current_srri_addr = 0x00000044,
323 .current_drri_addr = 0x00000048,
324 .ce_rri_low = 0x0024C004,
325 .ce_rri_high = 0x0024C008,
326 .host_ie_addr = 0x0000002c,
341 .ce_desc_meta_data_mask = 0xFFF0,
346 .msb = 0x00000010,
347 .lsb = 0x00000010,
352 .msb = 0x00000011,
353 .lsb = 0x00000011,
358 .msb = 0x0000000f,
359 .lsb = 0x00000000,
360 .mask = GENMASK(15, 0),
364 .addr = 0x00000010,
365 .hw_mask = 0x0007ffff,
366 .sw_mask = 0x0007ffff,
367 .hw_wr_mask = 0x00000000,
368 .sw_wr_mask = 0x0007ffff,
369 .reset_mask = 0xffffffff,
370 .reset = 0x00000080,
377 .msb = 0x00000003,
378 .lsb = 0x00000003,
383 .msb = 0x00000000,
384 .mask = GENMASK(0, 0),
385 .status_reset = 0x00000000,
390 .msb = 0x00000000,
391 .lsb = 0x00000000,
392 .mask = GENMASK(0, 0),
396 .copy_complete_reset = 0x00000000,
401 .dstr_lmask = 0x00000010,
402 .dstr_hmask = 0x00000008,
403 .srcr_lmask = 0x00000004,
404 .srcr_hmask = 0x00000002,
405 .cc_mask = 0x00000001,
406 .wm_mask = 0x0000001E,
407 .addr = 0x00000030,
411 .axi_err = 0x00000400,
412 .dstr_add_err = 0x00000200,
413 .srcr_len_err = 0x00000100,
414 .dstr_mlen_vio = 0x00000080,
415 .dstr_overflow = 0x00000040,
416 .srcr_overflow = 0x00000020,
417 .err_mask = 0x000007E0,
418 .addr = 0x00000038,
422 .msb = 0x0000001f,
423 .lsb = 0x00000010,
428 .msb = 0x0000000f,
429 .lsb = 0x00000000,
430 .mask = GENMASK(15, 0),
434 .addr = 0x0000004c,
435 .low_rst = 0x00000000,
436 .high_rst = 0x00000000,
442 .lsb = 0x00000010,
447 .msb = 0x0000000f,
448 .lsb = 0x00000000,
449 .mask = GENMASK(15, 0),
453 .addr = 0x00000050,
454 .low_rst = 0x00000000,
455 .high_rst = 0x00000000,
461 .sr_base_addr_lo = 0x00000000,
462 .sr_size_addr = 0x00000004,
463 .dr_base_addr_lo = 0x00000008,
464 .dr_size_addr = 0x0000000c,
465 .ce_cmd_addr = 0x00000018,
466 .misc_ie_addr = 0x00000034,
467 .sr_wr_index_addr = 0x0000003c,
468 .dst_wr_index_addr = 0x00000040,
469 .current_srri_addr = 0x00000044,
470 .current_drri_addr = 0x00000048,
471 .host_ie_addr = 0x0000002c,
484 .div = 0xe,
485 .rnfrac = 0x2aaa8,
487 .refdiv = 0,
492 .div = 0x24,
493 .rnfrac = 0x2aaa8,
495 .refdiv = 0,
500 .div = 0x1d,
501 .rnfrac = 0x15551,
503 .refdiv = 0,
508 .div = 0x1b,
509 .rnfrac = 0x4ec4,
511 .refdiv = 0,
516 .div = 0x12,
517 .rnfrac = 0x34b49,
519 .refdiv = 0,
524 .div = 0x12,
525 .rnfrac = 0x15551,
527 .refdiv = 0,
532 .div = 0x12,
533 .rnfrac = 0x26665,
535 .refdiv = 0,
540 .div = 0x1b,
541 .rnfrac = 0x4ec4,
543 .refdiv = 0,
551 u32 cc_fix = 0; in ath10k_hw_fill_survey_time()
552 u32 rcc_fix = 0; in ath10k_hw_fill_survey_time()
564 cc_fix = 0x7fffffff; in ath10k_hw_fill_survey_time()
570 cc_fix = 0x7fffffff; in ath10k_hw_fill_survey_time()
573 rcc_fix = 0x7fffffff; in ath10k_hw_fill_survey_time()
626 if (value < 0) in ath10k_hw_qca988x_set_coverage_class()
699 * coverage class is larger than 0. This is important as we need to in ath10k_hw_qca988x_set_coverage_class()
706 if (value > 0) { in ath10k_hw_qca988x_set_coverage_class()
709 fw_dbglog_mask = ~0; in ath10k_hw_qca988x_set_coverage_class()
737 * Return: 0 if successfully enable the pll, otherwise EINVAL
749 if (ar->regs->core_clk_div_address == 0 || in ath10k_hw_qca6174_enable_pll_clock()
750 ar->regs->cpu_pll_init_address == 0 || in ath10k_hw_qca6174_enable_pll_clock()
751 ar->regs->cpu_speed_address == 0) in ath10k_hw_qca6174_enable_pll_clock()
841 } while (wait_limit > 0); in ath10k_hw_qca6174_enable_pll_clock()
853 reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS); in ath10k_hw_qca6174_enable_pll_clock()
872 } while (wait_limit > 0); in ath10k_hw_qca6174_enable_pll_clock()
913 return 0; in ath10k_hw_qca6174_enable_pll_clock()
927 * 2. Target address( 0 ~ 00100000 & 0x00400000~0x00500000)
952 "failed to download the first %d bytes segment to address:0x%x: %d\n", in ath10k_hw_diag_segment_msb_download()
966 "failed to download the second %d bytes segment to address:0x%x: %d\n", in ath10k_hw_diag_segment_msb_download()
976 "failed to download the only %d bytes segment to address:0x%x: %d\n", in ath10k_hw_diag_segment_msb_download()
1009 u32 base_addr = 0; in ath10k_hw_diag_fast_download()
1010 u32 base_len = 0; in ath10k_hw_diag_fast_download()
1011 u32 left = 0; in ath10k_hw_diag_fast_download()
1014 int ret = 0; in ath10k_hw_diag_fast_download()
1025 "Not a supported firmware, magic_num:0x%x\n", in ath10k_hw_diag_fast_download()
1030 if (hdr->file_flags != 0) { in ath10k_hw_diag_fast_download()
1032 "Not a supported firmware, file_flags:0x%x\n", in ath10k_hw_diag_fast_download()
1040 while (left > 0) { in ath10k_hw_diag_fast_download()
1056 base_len = 0; in ath10k_hw_diag_fast_download()
1060 base_len = 0; in ath10k_hw_diag_fast_download()
1062 ret = 0; in ath10k_hw_diag_fast_download()
1100 if (ret == 0) in ath10k_hw_diag_fast_download()
1120 int pad_bytes = 0; in ath10k_get_htt_tx_data_rssi_pad()
1124 sizeof(extd.msdus_rssi[0]); in ath10k_get_htt_tx_data_rssi_pad()
1127 pad_bytes += sizeof(extd.t_stamp) / sizeof(extd.msdus_rssi[0]); in ath10k_get_htt_tx_data_rssi_pad()