75 	u8 __iomem *plx;	/* PLX PCI9060 virtual base address */  member
252         while((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) {  in wanxl_intr()
254 		writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);  in wanxl_intr()
300 	       port->card->plx + PLX_DOORBELL_TO_CARD);  in wanxl_xmit()
395 	u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;  in wanxl_open()
437 	       port->card->plx + PLX_DOORBELL_TO_CARD);  in wanxl_close()
483 	writel(cmd, card->plx + PLX_MAILBOX_1);  in wanxl_puts_command()
485 		if (readl(card->plx + PLX_MAILBOX_1) == 0)  in wanxl_puts_command()
498 	u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET;  in wanxl_reset()
500 	writel(0x80, card->plx + PLX_MAILBOX_0);  in wanxl_reset()
501 	writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);  in wanxl_reset()
502 	readl(card->plx + PLX_CONTROL); /* wait for posted write */  in wanxl_reset()
504 	writel(old_value, card->plx + PLX_CONTROL);  in wanxl_reset()
505 	readl(card->plx + PLX_CONTROL); /* wait for posted write */  in wanxl_reset()
534 	if (card->plx)  in wanxl_pci_remove_one()
535 		iounmap(card->plx);  in wanxl_pci_remove_one()
639 	card->plx = ioremap(plx_phy, 0x70);  in wanxl_pci_init_one()
640 	if (!card->plx) {  in wanxl_pci_init_one()
651 	while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) {  in wanxl_pci_init_one()
675 	ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK;  in wanxl_pci_init_one()
725 	writel(0, card->plx + PLX_MAILBOX_5);  in wanxl_pci_init_one()
735 		if ((stat = readl(card->plx + PLX_MAILBOX_5)) != 0)  in wanxl_pci_init_one()